mirror of
https://github.com/FFmpeg/FFmpeg.git
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a1bfb5290e
This is currently 64-bit only because the stack spilling code would not assemble on RV32I (and it would corrupt s0 and s1 on RV128I, in theory). This could be added later in the unlikely that someone wants it.
158 lines
3.9 KiB
ArmAsm
158 lines
3.9 KiB
ArmAsm
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_shuffle_bytes_0321_rvv, zve32x
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addi t1, a0, 3
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addi t2, a0, 2
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addi t3, a0, 1
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1:
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srai a2, a2, 2
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li t4, 4
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2:
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vsetvli t0, a2, e8, m1, ta, ma
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sub a2, a2, t0
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vlse8.v v8, (a0), t4
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sh2add a0, t0, a0
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vlse8.v v9, (t1), t4
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sh2add t1, t0, t1
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vlse8.v v10, (t2), t4
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sh2add t2, t0, t2
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vlse8.v v11, (t3), t4
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sh2add t3, t0, t3
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vsseg4e8.v v8, (a1)
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sh2add a1, t0, a1
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bnez a2, 2b
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ret
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endfunc
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func ff_shuffle_bytes_2103_rvv, zve32x
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addi t1, a0, 1
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addi t2, a0, 0
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addi t3, a0, 3
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addi a0, a0, 2
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j 1b
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endfunc
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func ff_shuffle_bytes_1230_rvv, zve32x
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addi t1, a0, 2
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addi t2, a0, 3
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addi t3, a0, 0
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addi a0, a0, 1
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j 1b
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endfunc
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func ff_shuffle_bytes_3012_rvv, zve32x
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addi t1, a0, 0
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addi t2, a0, 1
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addi t3, a0, 2
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addi a0, a0, 3
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j 1b
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endfunc
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func ff_shuffle_bytes_3210_rvv, zve32x
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addi t1, a0, 2
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addi t2, a0, 1
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addi t3, a0, 0
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addi a0, a0, 3
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j 1b
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endfunc
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func ff_interleave_bytes_rvv, zve32x
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1:
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mv t0, a0
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mv t1, a1
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mv t2, a2
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mv t3, a3
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addi a4, a4, -1
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2:
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vsetvli t4, t3, e8, ta, ma
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sub t3, t3, t4
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vle8.v v8, (t0)
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add t0, t4, t0
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vle8.v v9, (t1)
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add t1, t4, t1
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vsseg2e8.v v8, (t2)
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sh1add t2, t4, t2
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bnez t4, 2b
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add a0, a0, a5
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add a1, a1, a6
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add a2, a2, a7
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bnez a4, 1b
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ret
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endfunc
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#if (__riscv_xlen == 64)
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.macro yuy2_to_i422p v_y0, v_y1, v_u, v_v
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addi sp, sp, -16
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sd s0, (sp)
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sd s1, 8(sp)
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addi a4, a4, 1
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lw s0, 16(sp)
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srai a4, a4, 1 // pixel width -> chroma width
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li s1, 2
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1:
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mv t4, a4
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mv t3, a3
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mv t0, a0
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addi t6, a0, 1
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mv t1, a1
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mv t2, a2
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addi a5, a5, -1
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2:
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vsetvli t5, t4, e8, m1, ta, ma
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sub t4, t4, t5
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vlseg4e8.v v8, (t3)
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sh2add t3, t5, t3
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vsse8.v \v_y0, (t0), s1
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sh1add t0, t5, t0
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vsse8.v \v_y1, (t6), s1
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sh1add t6, t5, t6
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vse8.v \v_u, (t1)
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add t1, t5, t1
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vse8.v \v_v, (t2)
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add t2, t5, t2
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bnez t4, 2b
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add a3, a3, s0
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add a0, a0, a6
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add a1, a1, a7
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add a2, a2, a7
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bnez a5, 1b
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ld s1, 8(sp)
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ld s0, (sp)
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addi sp, sp, 16
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ret
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.endm
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func ff_uyvytoyuv422_rvv, zve32x
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yuy2_to_i422p v9, v11, v8, v10
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endfunc
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func ff_yuyvtoyuv422_rvv, zve32x
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yuy2_to_i422p v8, v10, v9, v11
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endfunc
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#endif
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