mirror of
https://github.com/FFmpeg/FFmpeg.git
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233066e85a
This is pretty much the same as for lpc16, though it only improves half as large prediction orders. With 128-bit vectors, this gives: C V old V new 1 69.2 181.5 95.5 2 107.7 180.7 95.2 3 145.5 180.0 103.5 4 183.0 179.2 102.7 5 220.7 178.5 128.0 6 257.7 194.0 127.5 7 294.5 193.7 126.7 8 331.0 193.0 126.5 Larger prediction orders see no significant changes at that size.
582 lines
14 KiB
ArmAsm
582 lines
14 KiB
ArmAsm
/*
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* Copyright © 2023 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_flac_lpc16_rvv, zve32x, zbb
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vtype_vli t0, a2, t2, e32, ta, ma
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vsetvl zero, a2, t0
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vle32.v v8, (a1)
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sub a4, a4, a2
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vle32.v v16, (a0)
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sh2add a0, a2, a0
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vmv.s.x v0, zero
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1:
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vmul.vv v24, v8, v16
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lw t0, (a0)
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vredsum.vs v24, v24, v0
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addi a4, a4, -1
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vmv.x.s t1, v24
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sra t1, t1, a3
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add t0, t0, t1
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vslide1down.vx v16, v16, t0
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sw t0, (a0)
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addi a0, a0, 4
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bnez a4, 1b
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ret
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endfunc
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#if (__riscv_xlen == 64)
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func ff_flac_lpc32_rvv, zve64x
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addi t2, a2, -16
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ble t2, zero, ff_flac_lpc32_rvv_simple
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vsetivli zero, 1, e64, m1, ta, ma
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vmv.s.x v0, zero
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vsetvli zero, a2, e32, m8, ta, ma
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vle32.v v8, (a1)
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sub a4, a4, a2
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vle32.v v16, (a0)
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sh2add a0, a2, a0
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1:
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vsetvli zero, a2, e32, m4, ta, ma
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vwmul.vv v24, v8, v16
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vsetvli zero, t2, e32, m4, tu, ma
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vwmacc.vv v24, v12, v20
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vsetvli zero, a2, e64, m8, ta, ma
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vredsum.vs v24, v24, v0
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lw t0, (a0)
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addi a4, a4, -1
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vmv.x.s t1, v24
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vsetvli zero, a2, e32, m8, ta, ma
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sra t1, t1, a3
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add t0, t0, t1
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vslide1down.vx v16, v16, t0
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sw t0, (a0)
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addi a0, a0, 4
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bnez a4, 1b
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ret
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endfunc
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func ff_flac_lpc32_rvv_simple, zve64x, zbb
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vtype_vli t3, a2, t1, e64, ta, ma
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vntypei t2, t3
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vsetvl zero, a2, t3 // e64
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vmv.s.x v0, zero
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vsetvl zero, zero, t2 // e32
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vle32.v v8, (a1)
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sub a4, a4, a2
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vle32.v v16, (a0)
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sh2add a0, a2, a0
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1:
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vwmul.vv v24, v8, v16
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vsetvl zero, zero, t3 // e64
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vredsum.vs v24, v24, v0
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lw t0, (a0)
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addi a4, a4, -1
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vmv.x.s t1, v24
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vsetvl zero, zero, t2 // e32
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sra t1, t1, a3
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add t0, t0, t1
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vslide1down.vx v16, v16, t0
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sw t0, (a0)
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addi a0, a0, 4
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bnez a4, 1b
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ret
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endfunc
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#endif
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func ff_flac_wasted32_rvv, zve32x
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1:
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vsetvli t0, a2, e32, m8, ta, ma
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vle32.v v8, (a0)
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sub a2, a2, t0
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vsll.vx v8, v8, a1
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vse32.v v8, (a0)
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sh2add a0, t0, a0
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bnez a2, 1b
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ret
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endfunc
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func ff_flac_wasted33_rvv, zve64x
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srli t0, a2, 5
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li t1, 1
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bnez t0, 2f
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sll a2, t1, a2
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1:
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vsetvli t0, a3, e32, m4, ta, ma
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vle32.v v8, (a1)
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sub a3, a3, t0
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vwmulsu.vx v16, v8, a2
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sh2add a1, t0, a1
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vse64.v v16, (a0)
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sh3add a0, t0, a0
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bnez a3, 1b
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ret
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2: // Pessimistic case: wasted >= 32
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vsetvli t0, a3, e32, m4, ta, ma
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vle32.v v8, (a1)
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sub a3, a3, t0
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vwcvtu.x.x.v v16, v8
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sh2add a1, t0, a1
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vsetvli zero, zero, e64, m8, ta, ma
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vsll.vx v16, v16, a2
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vse64.v v16, (a0)
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sh3add a0, t0, a0
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bnez a3, 2b
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ret
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endfunc
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#if (__riscv_xlen == 64)
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func ff_flac_decorrelate_indep2_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m8, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v8, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vsll.vx v8, v8, a4
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vsetvli zero, zero, e16, m4, ta, ma
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vncvt.x.x.w v16, v0
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vncvt.x.x.w v20, v8
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vsseg2e16.v v16, (a0)
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sh2add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_indep4_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld t1, 16(a1)
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ld t2, 24(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m4, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v4, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vle32.v v8, (t1)
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sh2add t1, t0, t1
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vsll.vx v4, v4, a4
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vle32.v v12, (t2)
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sh2add t2, t0, t2
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vsll.vx v8, v8, a4
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vsll.vx v12, v12, a4
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vsetvli zero, zero, e16, m2, ta, ma
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vncvt.x.x.w v16, v0
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vncvt.x.x.w v18, v4
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vncvt.x.x.w v20, v8
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vncvt.x.x.w v22, v12
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vsseg4e16.v v16, (a0)
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sh3add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_indep6_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld t1, 16(a1)
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ld t2, 24(a1)
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ld t3, 32(a1)
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ld t4, 40(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m2, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v2, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vle32.v v4, (t1)
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sh2add t1, t0, t1
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vsll.vx v2, v2, a4
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vle32.v v6, (t2)
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sh2add t2, t0, t2
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vsll.vx v4, v4, a4
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vle32.v v8, (t3)
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sh2add t3, t0, t3
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vsll.vx v6, v6, a4
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vle32.v v10, (t4)
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sh2add t4, t0, t4
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vsll.vx v8, v8, a4
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slli t0, t0, 2
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vsll.vx v10, v10, a4
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sh1add t0, t0, t0 // t0 *= 3
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vsetvli zero, zero, e16, m1, ta, ma
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vncvt.x.x.w v16, v0
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vncvt.x.x.w v17, v2
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vncvt.x.x.w v18, v4
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vncvt.x.x.w v19, v6
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vncvt.x.x.w v20, v8
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vncvt.x.x.w v21, v10
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vsseg6e16.v v16, (a0)
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add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_indep8_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld t1, 16(a1)
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ld t2, 24(a1)
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ld t3, 32(a1)
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ld t4, 40(a1)
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ld t5, 48(a1)
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ld t6, 56(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m2, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v2, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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vle32.v v4, (t1)
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sh2add a2, t0, a2
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vsll.vx v2, v2, a4
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sh2add t1, t0, t1
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vle32.v v6, (t2)
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vsll.vx v4, v4, a4
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sh2add t2, t0, t2
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vle32.v v8, (t3)
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sh2add t3, t0, t3
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vsll.vx v6, v6, a4
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vle32.v v10, (t4)
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sh2add t4, t0, t4
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vsll.vx v8, v8, a4
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vle32.v v12, (t5)
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sh2add t5, t0, t5
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vsll.vx v10, v10, a4
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vle32.v v14, (t6)
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sh2add t6, t0, t6
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vsll.vx v12, v12, a4
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slli t0, t0, 4
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vsll.vx v14, v14, a4
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vsetvli zero, zero, e16, m1, ta, ma
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vncvt.x.x.w v16, v0
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vncvt.x.x.w v17, v2
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vncvt.x.x.w v18, v4
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vncvt.x.x.w v19, v6
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vncvt.x.x.w v20, v8
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vncvt.x.x.w v21, v10
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vncvt.x.x.w v22, v12
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vncvt.x.x.w v23, v14
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vsseg8e16.v v16, (a0)
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add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_ls_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m8, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v8, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vsll.vx v8, v8, a4
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vsub.vv v8, v0, v8
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vsetvli zero, zero, e16, m4, ta, ma
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vncvt.x.x.w v16, v0
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vncvt.x.x.w v20, v8
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vsseg2e16.v v16, (a0)
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sh2add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_rs_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m8, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v8, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vsll.vx v8, v8, a4
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vadd.vv v0, v0, v8
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vsetvli zero, zero, e16, m4, ta, ma
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vncvt.x.x.w v16, v0
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vncvt.x.x.w v20, v8
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vsseg2e16.v v16, (a0)
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sh2add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_ms_16_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m8, ta, ma
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vle32.v v8, (a2)
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sub a3, a3, t0
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vle32.v v0, (a1)
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sh2add a1, t0, a1
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vsra.vi v16, v8, 1
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sh2add a2, t0, a2
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vsub.vv v24, v0, v16
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vadd.vv v16, v24, v8
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vsll.vx v8, v24, a4
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vsll.vx v0, v16, a4
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vsetvli zero, zero, e16, m4, ta, ma
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vncvt.x.x.w v0, v0
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vncvt.x.x.w v4, v8
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vsseg2e16.v v0, (a0)
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sh2add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_indep2_32_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m4, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v4, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vsll.vx v4, v4, a4
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vsseg2e32.v v0, (a0)
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sh3add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_indep4_32_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld t1, 16(a1)
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ld t2, 24(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m2, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v2, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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vle32.v v4, (t1)
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sh2add t1, t0, t1
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vsll.vx v2, v2, a4
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vle32.v v6, (t2)
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sh2add t2, t0, t2
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vsll.vx v4, v4, a4
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slli t0, t0, 4
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vsll.vx v6, v6, a4
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vsseg4e32.v v0, (a0)
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add a0, t0, a0
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bnez a3, 1b
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ret
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endfunc
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func ff_flac_decorrelate_indep6_32_rvv, zve32x
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ld a0, (a0)
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ld a2, 8(a1)
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ld t1, 16(a1)
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ld t2, 24(a1)
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ld t3, 32(a1)
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ld t4, 40(a1)
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ld a1, (a1)
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1:
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vsetvli t0, a3, e32, m1, ta, ma
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vle32.v v0, (a1)
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sub a3, a3, t0
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vle32.v v1, (a2)
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sh2add a1, t0, a1
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vsll.vx v0, v0, a4
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sh2add a2, t0, a2
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|
vle32.v v2, (t1)
|
|
sh2add t1, t0, t1
|
|
vsll.vx v1, v1, a4
|
|
vle32.v v3, (t2)
|
|
sh2add t2, t0, t2
|
|
vsll.vx v2, v2, a4
|
|
vle32.v v4, (t3)
|
|
sh2add t3, t0, t3
|
|
vsll.vx v3, v3, a4
|
|
vle32.v v5, (t4)
|
|
sh2add t4, t0, t4
|
|
vsll.vx v4, v4, a4
|
|
slli t0, t0, 3
|
|
vsll.vx v5, v5, a4
|
|
sh1add t0, t0, t0 // t0 *= 3
|
|
vsseg6e32.v v0, (a0)
|
|
add a0, t0, a0
|
|
bnez a3, 1b
|
|
|
|
ret
|
|
endfunc
|
|
|
|
func ff_flac_decorrelate_indep8_32_rvv, zve32x
|
|
ld a0, (a0)
|
|
ld a2, 8(a1)
|
|
ld t1, 16(a1)
|
|
ld t2, 24(a1)
|
|
ld t3, 32(a1)
|
|
ld t4, 40(a1)
|
|
ld t5, 48(a1)
|
|
ld t6, 56(a1)
|
|
ld a1, (a1)
|
|
1:
|
|
vsetvli t0, a3, e32, m1, ta, ma
|
|
vle32.v v0, (a1)
|
|
sub a3, a3, t0
|
|
vle32.v v1, (a2)
|
|
sh2add a1, t0, a1
|
|
vsll.vx v0, v0, a4
|
|
vle32.v v2, (t1)
|
|
sh2add a2, t0, a2
|
|
vsll.vx v1, v1, a4
|
|
sh2add t1, t0, t1
|
|
vle32.v v3, (t2)
|
|
vsll.vx v2, v2, a4
|
|
sh2add t2, t0, t2
|
|
vle32.v v4, (t3)
|
|
sh2add t3, t0, t3
|
|
vsll.vx v3, v3, a4
|
|
vle32.v v5, (t4)
|
|
sh2add t4, t0, t4
|
|
vsll.vx v4, v4, a4
|
|
vle32.v v6, (t5)
|
|
sh2add t5, t0, t5
|
|
vsll.vx v5, v5, a4
|
|
vle32.v v7, (t6)
|
|
sh2add t6, t0, t6
|
|
vsll.vx v6, v6, a4
|
|
slli t0, t0, 5
|
|
vsll.vx v7, v7, a4
|
|
vsseg8e32.v v0, (a0)
|
|
add a0, t0, a0
|
|
bnez a3, 1b
|
|
|
|
ret
|
|
endfunc
|
|
|
|
func ff_flac_decorrelate_ls_32_rvv, zve32x
|
|
ld a0, (a0)
|
|
ld a2, 8(a1)
|
|
ld a1, (a1)
|
|
1:
|
|
vsetvli t0, a3, e32, m4, ta, ma
|
|
vle32.v v0, (a1)
|
|
sub a3, a3, t0
|
|
vle32.v v4, (a2)
|
|
sh2add a1, t0, a1
|
|
vsll.vx v0, v0, a4
|
|
sh2add a2, t0, a2
|
|
vsll.vx v4, v4, a4
|
|
vsub.vv v4, v0, v4
|
|
vsseg2e32.v v0, (a0)
|
|
sh3add a0, t0, a0
|
|
bnez a3, 1b
|
|
|
|
ret
|
|
endfunc
|
|
|
|
func ff_flac_decorrelate_rs_32_rvv, zve32x
|
|
ld a0, (a0)
|
|
ld a2, 8(a1)
|
|
ld a1, (a1)
|
|
1:
|
|
vsetvli t0, a3, e32, m4, ta, ma
|
|
vle32.v v0, (a1)
|
|
sub a3, a3, t0
|
|
vle32.v v4, (a2)
|
|
sh2add a1, t0, a1
|
|
vsll.vx v0, v0, a4
|
|
sh2add a2, t0, a2
|
|
vsll.vx v4, v4, a4
|
|
vadd.vv v0, v0, v4
|
|
vsseg2e32.v v0, (a0)
|
|
sh3add a0, t0, a0
|
|
bnez a3, 1b
|
|
|
|
ret
|
|
endfunc
|
|
|
|
func ff_flac_decorrelate_ms_32_rvv, zve32x
|
|
ld a0, (a0)
|
|
ld a2, 8(a1)
|
|
ld a1, (a1)
|
|
1:
|
|
vsetvli t0, a3, e32, m4, ta, ma
|
|
vle32.v v4, (a2)
|
|
sub a3, a3, t0
|
|
vle32.v v0, (a1)
|
|
sh2add a1, t0, a1
|
|
vsra.vi v8, v4, 1
|
|
sh2add a2, t0, a2
|
|
vsub.vv v12, v0, v8
|
|
vadd.vv v8, v12, v4
|
|
vsll.vx v4, v12, a4
|
|
vsll.vx v0, v8, a4
|
|
vsseg2e32.v v0, (a0)
|
|
sh3add a0, t0, a0
|
|
bnez a3, 1b
|
|
|
|
ret
|
|
endfunc
|
|
#endif
|