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0724b4a16d
* commit '62844c3fd66940c7747e9b2bb7804e265319f43f': h264: Integrate clear_blocks calls with IDCT Conflicts: libavcodec/arm/h264idct_neon.S libavcodec/h264idct_template.c libavcodec/x86/h264_idct.asm Merged-by: Michael Niedermayer <michaelni@gmx.at>
414 lines
14 KiB
ArmAsm
414 lines
14 KiB
ArmAsm
/*
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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function ff_h264_idct_add_neon, export=1
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vld1.64 {d0-d3}, [r1,:128]
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vmov.i16 q15, #0
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vswp d1, d2
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vst1.16 {q15}, [r1,:128]!
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vadd.i16 d4, d0, d1
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vst1.16 {q15}, [r1,:128]!
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vshr.s16 q8, q1, #1
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vsub.i16 d5, d0, d1
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vadd.i16 d6, d2, d17
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vsub.i16 d7, d16, d3
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vadd.i16 q0, q2, q3
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vsub.i16 q1, q2, q3
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vtrn.16 d0, d1
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vtrn.16 d3, d2
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vtrn.32 d0, d3
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vtrn.32 d1, d2
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vadd.i16 d4, d0, d3
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vld1.32 {d18[0]}, [r0,:32], r2
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vswp d1, d3
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vshr.s16 q8, q1, #1
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vld1.32 {d19[1]}, [r0,:32], r2
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vsub.i16 d5, d0, d1
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vld1.32 {d18[1]}, [r0,:32], r2
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vadd.i16 d6, d16, d3
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vld1.32 {d19[0]}, [r0,:32], r2
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vsub.i16 d7, d2, d17
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sub r0, r0, r2, lsl #2
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vadd.i16 q0, q2, q3
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vsub.i16 q1, q2, q3
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vrshr.s16 q0, q0, #6
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vrshr.s16 q1, q1, #6
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vaddw.u8 q0, q0, d18
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vaddw.u8 q1, q1, d19
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vqmovun.s16 d0, q0
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vqmovun.s16 d1, q1
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vst1.32 {d0[0]}, [r0,:32], r2
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vst1.32 {d1[1]}, [r0,:32], r2
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vst1.32 {d0[1]}, [r0,:32], r2
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vst1.32 {d1[0]}, [r0,:32], r2
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sub r1, r1, #32
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bx lr
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endfunc
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function ff_h264_idct_dc_add_neon, export=1
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mov r3, #0
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vld1.16 {d2[],d3[]}, [r1,:16]
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strh r3, [r1]
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vrshr.s16 q1, q1, #6
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vld1.32 {d0[0]}, [r0,:32], r2
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vld1.32 {d0[1]}, [r0,:32], r2
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vaddw.u8 q2, q1, d0
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vld1.32 {d1[0]}, [r0,:32], r2
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vld1.32 {d1[1]}, [r0,:32], r2
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vaddw.u8 q1, q1, d1
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vqmovun.s16 d0, q2
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vqmovun.s16 d1, q1
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sub r0, r0, r2, lsl #2
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vst1.32 {d0[0]}, [r0,:32], r2
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vst1.32 {d0[1]}, [r0,:32], r2
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vst1.32 {d1[0]}, [r0,:32], r2
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vst1.32 {d1[1]}, [r0,:32], r2
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bx lr
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endfunc
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function ff_h264_idct_add16_neon, export=1
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push {r4-r8,lr}
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mov r4, r0
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mov r5, r1
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mov r1, r2
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mov r2, r3
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ldr r6, [sp, #24]
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movrel r7, scan8
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mov ip, #16
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1: ldrb r8, [r7], #1
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ldr r0, [r5], #4
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ldrb r8, [r6, r8]
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subs r8, r8, #1
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blt 2f
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ldrsh lr, [r1]
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add r0, r0, r4
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it ne
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movne lr, #0
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cmp lr, #0
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ite ne
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adrne lr, ff_h264_idct_dc_add_neon + CONFIG_THUMB
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adreq lr, ff_h264_idct_add_neon + CONFIG_THUMB
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blx lr
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2: subs ip, ip, #1
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add r1, r1, #32
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bne 1b
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pop {r4-r8,pc}
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endfunc
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function ff_h264_idct_add16intra_neon, export=1
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push {r4-r8,lr}
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mov r4, r0
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mov r5, r1
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mov r1, r2
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mov r2, r3
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ldr r6, [sp, #24]
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movrel r7, scan8
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mov ip, #16
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1: ldrb r8, [r7], #1
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ldr r0, [r5], #4
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ldrb r8, [r6, r8]
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add r0, r0, r4
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cmp r8, #0
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ldrsh r8, [r1]
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iteet ne
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adrne lr, ff_h264_idct_add_neon + CONFIG_THUMB
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adreq lr, ff_h264_idct_dc_add_neon + CONFIG_THUMB
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cmpeq r8, #0
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blxne lr
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subs ip, ip, #1
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add r1, r1, #32
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bne 1b
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pop {r4-r8,pc}
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endfunc
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function ff_h264_idct_add8_neon, export=1
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push {r4-r10,lr}
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ldm r0, {r4,r9}
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add r5, r1, #16*4
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add r1, r2, #16*32
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mov r2, r3
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mov r10, r1
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ldr r6, [sp, #32]
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movrel r7, scan8+16
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mov r12, #0
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1: ldrb r8, [r7, r12]
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ldr r0, [r5, r12, lsl #2]
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ldrb r8, [r6, r8]
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add r0, r0, r4
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add r1, r10, r12, lsl #5
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cmp r8, #0
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ldrsh r8, [r1]
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iteet ne
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adrne lr, ff_h264_idct_add_neon + CONFIG_THUMB
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adreq lr, ff_h264_idct_dc_add_neon + CONFIG_THUMB
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cmpeq r8, #0
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blxne lr
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add r12, r12, #1
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cmp r12, #4
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itt eq
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moveq r12, #16
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moveq r4, r9
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cmp r12, #20
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blt 1b
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pop {r4-r10,pc}
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endfunc
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.macro idct8x8_cols pass
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.if \pass == 0
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qa .req q2
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qb .req q14
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vshr.s16 q2, q10, #1
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vadd.i16 q0, q8, q12
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vld1.16 {q14-q15},[r1,:128]
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vst1.16 {q3}, [r1,:128]!
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vst1.16 {q3}, [r1,:128]!
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vsub.i16 q1, q8, q12
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vshr.s16 q3, q14, #1
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vsub.i16 q2, q2, q14
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vadd.i16 q3, q3, q10
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.else
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qa .req q14
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qb .req q2
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vtrn.32 q8, q10
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vtrn.16 q12, q13
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vtrn.32 q9, q11
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vtrn.32 q12, q2
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vtrn.32 q13, q15
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vswp d21, d4
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vshr.s16 q14, q10, #1
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vswp d17, d24
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vshr.s16 q3, q2, #1
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vswp d19, d26
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vadd.i16 q0, q8, q12
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vswp d23, d30
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vsub.i16 q1, q8, q12
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vsub.i16 q14, q14, q2
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vadd.i16 q3, q3, q10
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.endif
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vadd.i16 q10, q1, qa
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vsub.i16 q12, q1, qa
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vadd.i16 q8, q0, q3
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vsub.i16 qb, q0, q3
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vsub.i16 q0, q13, q11
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vadd.i16 q1, q15, q9
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vsub.i16 qa, q15, q9
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vadd.i16 q3, q13, q11
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vsub.i16 q0, q0, q15
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vsub.i16 q1, q1, q11
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vadd.i16 qa, qa, q13
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vadd.i16 q3, q3, q9
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vshr.s16 q9, q9, #1
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vshr.s16 q11, q11, #1
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vshr.s16 q13, q13, #1
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vshr.s16 q15, q15, #1
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vsub.i16 q0, q0, q15
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vsub.i16 q1, q1, q11
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vadd.i16 qa, qa, q13
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vadd.i16 q3, q3, q9
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vshr.s16 q9, q0, #2
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vshr.s16 q11, q1, #2
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vshr.s16 q13, qa, #2
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vshr.s16 q15, q3, #2
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vsub.i16 q3, q3, q9
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vsub.i16 qa, q11, qa
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vadd.i16 q1, q1, q13
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vadd.i16 q0, q0, q15
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.if \pass == 0
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vsub.i16 q15, q8, q3
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vadd.i16 q8, q8, q3
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vadd.i16 q9, q10, q2
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vsub.i16 q2, q10, q2
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vtrn.16 q8, q9
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vadd.i16 q10, q12, q1
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vtrn.16 q2, q15
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vadd.i16 q11, q14, q0
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vsub.i16 q13, q12, q1
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vtrn.16 q10, q11
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vsub.i16 q12, q14, q0
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.else
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vsub.i16 q15, q8, q3
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vadd.i16 q8, q8, q3
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vadd.i16 q9, q10, q14
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vsub.i16 q14, q10, q14
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vadd.i16 q10, q12, q1
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vsub.i16 q13, q12, q1
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vadd.i16 q11, q2, q0
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vsub.i16 q12, q2, q0
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.endif
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.unreq qa
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.unreq qb
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.endm
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function ff_h264_idct8_add_neon, export=1
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vmov.i16 q3, #0
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vld1.16 {q8-q9}, [r1,:128]
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vst1.16 {q3}, [r1,:128]!
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vst1.16 {q3}, [r1,:128]!
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vld1.16 {q10-q11},[r1,:128]
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vst1.16 {q3}, [r1,:128]!
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vst1.16 {q3}, [r1,:128]!
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vld1.16 {q12-q13},[r1,:128]
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vst1.16 {q3}, [r1,:128]!
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vst1.16 {q3}, [r1,:128]!
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idct8x8_cols 0
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idct8x8_cols 1
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mov r3, r0
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vrshr.s16 q8, q8, #6
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vld1.8 {d0}, [r0,:64], r2
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vrshr.s16 q9, q9, #6
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vld1.8 {d1}, [r0,:64], r2
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vrshr.s16 q10, q10, #6
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vld1.8 {d2}, [r0,:64], r2
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vrshr.s16 q11, q11, #6
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vld1.8 {d3}, [r0,:64], r2
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vrshr.s16 q12, q12, #6
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vld1.8 {d4}, [r0,:64], r2
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vrshr.s16 q13, q13, #6
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vld1.8 {d5}, [r0,:64], r2
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vrshr.s16 q14, q14, #6
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vld1.8 {d6}, [r0,:64], r2
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vrshr.s16 q15, q15, #6
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vld1.8 {d7}, [r0,:64], r2
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vaddw.u8 q8, q8, d0
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vaddw.u8 q9, q9, d1
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vaddw.u8 q10, q10, d2
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vqmovun.s16 d0, q8
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vaddw.u8 q11, q11, d3
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vqmovun.s16 d1, q9
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vaddw.u8 q12, q12, d4
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vqmovun.s16 d2, q10
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vst1.8 {d0}, [r3,:64], r2
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vaddw.u8 q13, q13, d5
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vqmovun.s16 d3, q11
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vst1.8 {d1}, [r3,:64], r2
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vaddw.u8 q14, q14, d6
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vqmovun.s16 d4, q12
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vst1.8 {d2}, [r3,:64], r2
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vaddw.u8 q15, q15, d7
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vqmovun.s16 d5, q13
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vst1.8 {d3}, [r3,:64], r2
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vqmovun.s16 d6, q14
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vqmovun.s16 d7, q15
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vst1.8 {d4}, [r3,:64], r2
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vst1.8 {d5}, [r3,:64], r2
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vst1.8 {d6}, [r3,:64], r2
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vst1.8 {d7}, [r3,:64], r2
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sub r1, r1, #128
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bx lr
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endfunc
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function ff_h264_idct8_dc_add_neon, export=1
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mov r3, #0
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vld1.16 {d30[],d31[]},[r1,:16]
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strh r3, [r1]
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vld1.32 {d0}, [r0,:64], r2
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vrshr.s16 q15, q15, #6
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vld1.32 {d1}, [r0,:64], r2
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vld1.32 {d2}, [r0,:64], r2
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vaddw.u8 q8, q15, d0
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vld1.32 {d3}, [r0,:64], r2
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vaddw.u8 q9, q15, d1
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vld1.32 {d4}, [r0,:64], r2
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vaddw.u8 q10, q15, d2
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vld1.32 {d5}, [r0,:64], r2
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vaddw.u8 q11, q15, d3
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vld1.32 {d6}, [r0,:64], r2
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vaddw.u8 q12, q15, d4
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vld1.32 {d7}, [r0,:64], r2
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vaddw.u8 q13, q15, d5
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vaddw.u8 q14, q15, d6
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vaddw.u8 q15, q15, d7
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vqmovun.s16 d0, q8
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vqmovun.s16 d1, q9
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vqmovun.s16 d2, q10
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vqmovun.s16 d3, q11
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sub r0, r0, r2, lsl #3
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vst1.32 {d0}, [r0,:64], r2
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vqmovun.s16 d4, q12
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vst1.32 {d1}, [r0,:64], r2
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vqmovun.s16 d5, q13
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vst1.32 {d2}, [r0,:64], r2
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vqmovun.s16 d6, q14
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vst1.32 {d3}, [r0,:64], r2
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vqmovun.s16 d7, q15
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vst1.32 {d4}, [r0,:64], r2
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vst1.32 {d5}, [r0,:64], r2
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vst1.32 {d6}, [r0,:64], r2
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vst1.32 {d7}, [r0,:64], r2
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bx lr
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endfunc
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function ff_h264_idct8_add4_neon, export=1
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push {r4-r8,lr}
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mov r4, r0
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mov r5, r1
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mov r1, r2
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mov r2, r3
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ldr r6, [sp, #24]
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movrel r7, scan8
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mov r12, #16
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1: ldrb r8, [r7], #4
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ldr r0, [r5], #16
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ldrb r8, [r6, r8]
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subs r8, r8, #1
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blt 2f
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ldrsh lr, [r1]
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add r0, r0, r4
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it ne
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movne lr, #0
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cmp lr, #0
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ite ne
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adrne lr, ff_h264_idct8_dc_add_neon + CONFIG_THUMB
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adreq lr, ff_h264_idct8_add_neon + CONFIG_THUMB
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blx lr
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2: subs r12, r12, #4
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add r1, r1, #128
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bne 1b
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pop {r4-r8,pc}
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endfunc
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const scan8
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.byte 4+ 1*8, 5+ 1*8, 4+ 2*8, 5+ 2*8
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.byte 6+ 1*8, 7+ 1*8, 6+ 2*8, 7+ 2*8
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.byte 4+ 3*8, 5+ 3*8, 4+ 4*8, 5+ 4*8
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.byte 6+ 3*8, 7+ 3*8, 6+ 4*8, 7+ 4*8
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.byte 4+ 6*8, 5+ 6*8, 4+ 7*8, 5+ 7*8
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.byte 6+ 6*8, 7+ 6*8, 6+ 7*8, 7+ 7*8
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.byte 4+ 8*8, 5+ 8*8, 4+ 9*8, 5+ 9*8
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.byte 6+ 8*8, 7+ 8*8, 6+ 9*8, 7+ 9*8
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.byte 4+11*8, 5+11*8, 4+12*8, 5+12*8
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.byte 6+11*8, 7+11*8, 6+12*8, 7+12*8
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.byte 4+13*8, 5+13*8, 4+14*8, 5+14*8
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.byte 6+13*8, 7+13*8, 6+14*8, 7+14*8
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endconst
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