mirror of
https://github.com/FFmpeg/FFmpeg.git
synced 2024-12-23 12:43:46 +02:00
386 lines
12 KiB
NASM
386 lines
12 KiB
NASM
;******************************************************************************
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;* SIMD optimized Opus encoder DSP function
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;*
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;* Copyright (C) 2017 Ivan Kalvachev <ikalvachev@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "config.asm"
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%include "libavutil/x86/x86util.asm"
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%ifdef __NASM_VER__
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%use "smartalign"
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ALIGNMODE p6
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%endif
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SECTION_RODATA 64
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const_float_abs_mask: times 8 dd 0x7fffffff
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const_align_abs_edge: times 8 dd 0
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const_float_0_5: times 8 dd 0.5
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const_float_1: times 8 dd 1.0
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const_float_sign_mask: times 8 dd 0x80000000
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const_int32_offsets:
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%rep 8
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dd $-const_int32_offsets
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%endrep
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SECTION .text
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;
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; Setup High Register to be used
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; for holding memory constants
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;
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; %1 - the register to be used, assmues it is >= mm8
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; %2 - name of the constant.
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;
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; Subsequent opcodes are going to use the constant in the form
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; "addps m0, mm_const_name" and it would be turned into:
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; "addps m0, [const_name]" on 32 bit arch or
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; "addps m0, m8" on 64 bit arch
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%macro SET_HI_REG_MM_CONSTANT 3 ; movop, reg, const_name
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%if num_mmregs > 8
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%define mm_%3 %2
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%{1} %2, [%3] ; movaps m8, [const_name]
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%else
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%define mm_%3 [%3]
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%endif
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%endmacro
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;
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; Set Position Independent Code
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; Base address of a constant
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; %1 - the register to be used, if PIC is set
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; %2 - name of the constant.
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;
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; Subsequent opcode are going to use the base address in the form
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; "movaps m0, [pic_base_constant_name+r4]" and it would be turned into
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; "movaps m0, [r5 + r4]" if PIC is enabled
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; "movaps m0, [constant_name + r4]" if texrel are used
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%macro SET_PIC_BASE 3; reg, const_label
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%ifdef PIC
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%{1} %2, [%3] ; lea r5, [rip+const]
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%define pic_base_%3 %2
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%else
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%define pic_base_%3 %3
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%endif
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%endmacro
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%macro PULSES_SEARCH 1
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; m6 Syy_norm
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; m7 Sxy_norm
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addps m6, mm_const_float_0_5 ; Syy_norm += 1.0/2
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pxor m1, m1 ; max_idx
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xorps m3, m3 ; p_max
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xor r4d, r4d
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align 16
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%%distortion_search:
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movd xm2, dword r4d ; movd zero extends
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%ifidn %1,add
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movaps m4, [tmpY + r4] ; y[i]
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movaps m5, [tmpX + r4] ; X[i]
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%if USE_APPROXIMATION == 1
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xorps m0, m0
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cmpps m0, m0, m5, 4 ; m0 = (X[i] != 0.0)
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%endif
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addps m4, m6 ; m4 = Syy_new = y[i] + Syy_norm
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addps m5, m7 ; m5 = Sxy_new = X[i] + Sxy_norm
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%if USE_APPROXIMATION == 1
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andps m5, m0 ; if(X[i] == 0) Sxy_new = 0; Prevent aproximation error from setting pulses in array padding.
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%endif
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%else
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movaps m5, [tmpY + r4] ; m5 = y[i]
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xorps m0, m0 ; m0 = 0;
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cmpps m0, m0, m5, 1 ; m0 = (0<y)
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subps m4, m6, m5 ; m4 = Syy_new = Syy_norm - y[i]
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subps m5, m7, [tmpX + r4] ; m5 = Sxy_new = Sxy_norm - X[i]
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andps m5, m0 ; (0<y)?m5:0
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%endif
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%if USE_APPROXIMATION == 1
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rsqrtps m4, m4
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mulps m5, m4 ; m5 = p = Sxy_new*approx(1/sqrt(Syy) )
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%else
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mulps m5, m5
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divps m5, m4 ; m5 = p = Sxy_new*Sxy_new/Syy
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%endif
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VPBROADCASTD m2, xm2 ; m2=i (all lanes get same values, we add the offset-per-lane, later)
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cmpps m0, m3, m5, 1 ; m0 = (m3 < m5) ; (p_max < p) ; (p > p_max)
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maxps m3, m5 ; m3=max(p_max,p)
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; maxps here is faster than blendvps, despite blend having lower latency.
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pand m2, m0 ; This version seems faster than sse41 pblendvb
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pmaxsw m1, m2 ; SSE2 signed word, so it would work for N < 32768/4
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add r4d, mmsize
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cmp r4d, Nd
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jb %%distortion_search
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por m1, mm_const_int32_offsets ; max_idx offsets per individual lane (skipped in the inner loop)
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movdqa m4, m1 ; needed for the aligned y[max_idx]+=1; processing
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%if mmsize >= 32
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; Merge parallel maximums round 8 (4 vs 4)
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vextractf128 xm5, ym3, 1 ; xmm5 = ymm3[1x128] = ymm3[255..128b]
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cmpps xm0, xm3, xm5, 1 ; m0 = (m3 < m5) = ( p[0x128] < p[1x128] )
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vextracti128 xm2, ym1, 1 ; xmm2 = ymm1[1x128] = ymm1[255..128b]
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BLENDVPS xm3, xm5, xm0 ; max_idx = m0 ? max_idx[1x128] : max_idx[0x128]
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PBLENDVB xm1, xm2, xm0 ; p = m0 ? p[1x128] : p[0x128]
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%endif
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; Merge parallel maximums round 4 (2 vs 2)
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; m3=p[3210]
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movhlps xm5, xm3 ; m5=p[xx32]
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cmpps xm0, xm3, xm5, 1 ; m0 = (m3 < m5) = ( p[1,0] < p[3,2] )
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pshufd xm2, xm1, q3232
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BLENDVPS xm3, xm5, xm0 ; max_idx = m0 ? max_idx[3,2] : max_idx[1,0]
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PBLENDVB xm1, xm2, xm0 ; p = m0 ? p[3,2] : p[1,0]
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; Merge parallel maximums final round (1 vs 1)
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shufps xm0, xm3, xm3, q1111 ; m0 = m3[1] = p[1]
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cmpss xm0, xm3, 5 ; m0 = !(m0 >= m3) = !( p[1] >= p[0] )
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pshufd xm2, xm1, q1111
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PBLENDVB xm1, xm2, xm0
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movd dword r4d, xm1 ; zero extends to the rest of r4q
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VBROADCASTSS m3, [tmpX + r4]
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%{1}ps m7, m3 ; Sxy += X[max_idx]
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VBROADCASTSS m5, [tmpY + r4]
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%{1}ps m6, m5 ; Syy += Y[max_idx]
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; We have to update a single element in Y[i]
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; However writing 4 bytes and then doing 16 byte load in the inner loop
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; could cause a stall due to breaking write forwarding.
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VPBROADCASTD m1, xm1
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pcmpeqd m1, m1, m4 ; exactly 1 element matches max_idx and this finds it
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and r4d, ~(mmsize-1) ; align address down, so the value pointed by max_idx is inside a mmsize load
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movaps m5, [tmpY + r4] ; m5 = Y[y3...ym...y0]
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andps m1, mm_const_float_1 ; m1 = [ 0...1.0...0]
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%{1}ps m5, m1 ; m5 = Y[y3...ym...y0] +/- [0...1.0...0]
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movaps [tmpY + r4], m5 ; Y[max_idx] +-= 1.0;
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%endmacro
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;
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; We need one more register for
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; PIC relative addressing. Use this
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; to count it in cglobal
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;
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%ifdef PIC
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%define num_pic_regs 1
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%else
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%define num_pic_regs 0
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%endif
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;
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; Pyramid Vector Quantization Search implementation
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;
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; float * inX - Unaligned (SIMD) access, it will be overread,
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; but extra data is masked away.
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; int32 * outY - Should be aligned and padded buffer.
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; It is used as temp buffer.
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; uint32 K - Number of pulses to have after quantizations.
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; uint32 N - Number of vector elements. Must be 0 < N < 256
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;
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%macro PVQ_FAST_SEARCH 1
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cglobal pvq_search%1, 4, 5+num_pic_regs, 11, 256*4, inX, outY, K, N
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%define tmpX rsp
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%define tmpY outYq
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movaps m0, [const_float_abs_mask]
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shl Nd, 2 ; N *= sizeof(float); also 32 bit operation zeroes the high 32 bits in 64 bit mode.
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mov r4d, Nd
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neg r4d
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and r4d, mmsize-1
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SET_PIC_BASE lea, r5, const_align_abs_edge ; rip+const
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movups m2, [pic_base_const_align_abs_edge + r4 - mmsize]
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add Nd, r4d ; N = align(N, mmsize)
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lea r4d, [Nd - mmsize] ; N is rounded up (aligned up) to mmsize, so r4 can't become negative here, unless N=0.
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movups m1, [inXq + r4]
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andps m1, m2
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movaps [tmpX + r4], m1 ; Sx = abs( X[N-1] )
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align 16
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%%loop_abs_sum:
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sub r4d, mmsize
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jc %%end_loop_abs_sum
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movups m2, [inXq + r4]
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andps m2, m0
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movaps [tmpX + r4], m2 ; tmpX[i]=abs(X[i])
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addps m1, m2 ; Sx += abs(X[i])
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jmp %%loop_abs_sum
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align 16
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%%end_loop_abs_sum:
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HSUMPS m1, m2 ; m1 = Sx
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xorps m0, m0
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comiss xm0, xm1 ;
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jz %%zero_input ; if (Sx==0) goto zero_input
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cvtsi2ss xm0, dword Kd ; m0 = K
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%if USE_APPROXIMATION == 1
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rcpss xm1, xm1 ; m1 = approx(1/Sx)
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mulss xm0, xm1 ; m0 = K*(1/Sx)
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%else
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divss xm0, xm1 ; b = K/Sx
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; b = K/max_x
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%endif
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VBROADCASTSS m0, xm0
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lea r4d, [Nd - mmsize]
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pxor m5, m5 ; Sy ( Sum of abs( y[i]) )
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xorps m6, m6 ; Syy ( Sum of y[i]*y[i] )
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xorps m7, m7 ; Sxy ( Sum of X[i]*y[i] )
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align 16
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%%loop_guess:
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movaps m1, [tmpX + r4] ; m1 = X[i]
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mulps m2, m0, m1 ; m2 = res*X[i]
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cvtps2dq m2, m2 ; yt = (int)lrintf( res*X[i] )
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paddd m5, m2 ; Sy += yt
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cvtdq2ps m2, m2 ; yt = (float)yt
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mulps m1, m2 ; m1 = X[i]*yt
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movaps [tmpY + r4], m2 ; y[i] = m2
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addps m7, m1 ; Sxy += m1;
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mulps m2, m2 ; m2 = yt*yt
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addps m6, m2 ; Syy += m2
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sub r4d, mmsize
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jnc %%loop_guess
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HSUMPS m6, m1 ; Syy_norm
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HADDD m5, m4 ; pulses
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movd dword r4d, xm5 ; zero extends to the rest of r4q
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sub Kd, r4d ; K -= pulses , also 32 bit operation zeroes high 32 bit in 64 bit mode.
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jz %%finish ; K - pulses == 0
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SET_HI_REG_MM_CONSTANT movaps, m8, const_float_0_5
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SET_HI_REG_MM_CONSTANT movaps, m9, const_float_1
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SET_HI_REG_MM_CONSTANT movdqa, m10, const_int32_offsets
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; Use Syy/2 in distortion parameter calculations.
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; Saves pre and post-caclulation to correct Y[] values.
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; Same precision, since float mantisa is normalized.
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; The SQRT approximation does differ.
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HSUMPS m7, m0 ; Sxy_norm
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mulps m6, mm_const_float_0_5
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jc %%remove_pulses_loop ; K - pulses < 0
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align 16 ; K - pulses > 0
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%%add_pulses_loop:
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PULSES_SEARCH add ; m6 Syy_norm ; m7 Sxy_norm
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sub Kd, 1
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jnz %%add_pulses_loop
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addps m6, m6 ; Syy*=2
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jmp %%finish
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align 16
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%%remove_pulses_loop:
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PULSES_SEARCH sub ; m6 Syy_norm ; m7 Sxy_norm
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add Kd, 1
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jnz %%remove_pulses_loop
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addps m6, m6 ; Syy*=2
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align 16
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%%finish:
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lea r4d, [Nd - mmsize]
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movaps m2, [const_float_sign_mask]
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align 16
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%%restore_sign_loop:
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movaps m0, [tmpY + r4] ; m0 = Y[i]
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movups m1, [inXq + r4] ; m1 = X[i]
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andps m1, m2 ; m1 = sign(X[i])
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orps m0, m1 ; m0 = Y[i]*sign
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cvtps2dq m3, m0 ; m3 = (int)m0
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movaps [outYq + r4], m3
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sub r4d, mmsize
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jnc %%restore_sign_loop
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%%return:
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%if ARCH_X86_64 == 0 ; sbrdsp
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movss r0m, xm6 ; return (float)Syy_norm
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fld dword r0m
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%else
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movaps m0, m6 ; return (float)Syy_norm
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%endif
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RET
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align 16
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%%zero_input:
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lea r4d, [Nd - mmsize]
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xorps m0, m0
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%%zero_loop:
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movaps [outYq + r4], m0
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sub r4d, mmsize
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jnc %%zero_loop
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movaps m6, [const_float_1]
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jmp %%return
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%endmacro
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; if 1, use a float op that give half precision but execute for around 3 cycles.
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; On Skylake & Ryzen the division is much faster (around 11c/3),
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; that makes the full precision code about 2% slower.
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; Opus also does use rsqrt approximation in their intrinsics code.
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%define USE_APPROXIMATION 1
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INIT_XMM sse2
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PVQ_FAST_SEARCH _approx
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INIT_XMM sse4
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PVQ_FAST_SEARCH _approx
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%define USE_APPROXIMATION 0
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INIT_XMM avx
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PVQ_FAST_SEARCH _exact
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