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8dbe585641
This patch lets e.g. dsputil_init chose dsp functions with respect to the bit depth to decode. The naming scheme of bit depth dependent functions is <base name>_<bit depth>[_<prefix>] (i.e. the old clear_blocks_c is now named clear_blocks_8_c). Note: Some of the functions for high bit depth is not dependent on the bit depth, but only on the pixel size. This leaves some room for optimizing binary size. Preparatory patch for high bit depth h264 decoding support. Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
207 lines
6.4 KiB
C
207 lines
6.4 KiB
C
/*
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* Copyright (c) 2002 Brian Foley
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* Copyright (c) 2002 Dieter Shirley
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* Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/cpu.h"
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#include "libavcodec/dsputil.h"
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#include "dsputil_altivec.h"
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/* ***** WARNING ***** WARNING ***** WARNING ***** */
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/*
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clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
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cache line size not equal to 32 bytes.
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Fortunately all processor used by Apple up to at least the 7450 (aka second
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generation G4) use 32 bytes cache line.
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This is due to the use of the 'dcbz' instruction. It simply clear to zero a
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single cache line, so you need to know the cache line size to use it !
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It's absurd, but it's fast...
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update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
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size: 128 bytes. Oups.
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The semantic of dcbz was changed, it always clear 32 bytes. so the function
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below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
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which is defined to clear a cache line (as dcbz before). So we still can
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distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
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see <http://developer.apple.com/technotes/tn/tn2087.html>
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and <http://developer.apple.com/technotes/tn/tn2086.html>
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*/
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static void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
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{
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register int misal = ((unsigned long)blocks & 0x00000010);
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register int i = 0;
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#if 1
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if (misal) {
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((unsigned long*)blocks)[0] = 0L;
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((unsigned long*)blocks)[1] = 0L;
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((unsigned long*)blocks)[2] = 0L;
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((unsigned long*)blocks)[3] = 0L;
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i += 16;
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}
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for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
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__asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
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}
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if (misal) {
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((unsigned long*)blocks)[188] = 0L;
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((unsigned long*)blocks)[189] = 0L;
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((unsigned long*)blocks)[190] = 0L;
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((unsigned long*)blocks)[191] = 0L;
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i += 16;
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}
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#else
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memset(blocks, 0, sizeof(DCTELEM)*6*64);
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#endif
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}
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/* same as above, when dcbzl clear a whole 128B cache line
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i.e. the PPC970 aka G5 */
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#if HAVE_DCBZL
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static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
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{
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register int misal = ((unsigned long)blocks & 0x0000007f);
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register int i = 0;
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#if 1
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if (misal) {
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// we could probably also optimize this case,
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// but there's not much point as the machines
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// aren't available yet (2003-06-26)
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memset(blocks, 0, sizeof(DCTELEM)*6*64);
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}
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else
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for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
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__asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
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}
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#else
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memset(blocks, 0, sizeof(DCTELEM)*6*64);
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#endif
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}
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#else
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static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
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{
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memset(blocks, 0, sizeof(DCTELEM)*6*64);
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}
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#endif
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#if HAVE_DCBZL
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/* check dcbz report how many bytes are set to 0 by dcbz */
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/* update 24/06/2003 : replace dcbz by dcbzl to get
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the intended effect (Apple "fixed" dcbz)
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unfortunately this cannot be used unless the assembler
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knows about dcbzl ... */
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static long check_dcbzl_effect(void)
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{
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register char *fakedata = av_malloc(1024);
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register char *fakedata_middle;
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register long zero = 0;
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register long i = 0;
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long count = 0;
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if (!fakedata) {
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return 0L;
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}
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fakedata_middle = (fakedata + 512);
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memset(fakedata, 0xFF, 1024);
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/* below the constraint "b" seems to mean "Address base register"
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in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
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__asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
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for (i = 0; i < 1024 ; i ++) {
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if (fakedata[i] == (char)0)
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count++;
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}
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av_free(fakedata);
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return count;
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}
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#else
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static long check_dcbzl_effect(void)
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{
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return 0;
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}
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#endif
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static void prefetch_ppc(void *mem, int stride, int h)
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{
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register const uint8_t *p = mem;
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do {
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__asm__ volatile ("dcbt 0,%0" : : "r" (p));
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p+= stride;
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} while(--h);
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}
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void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
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{
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const int h264_high_depth = avctx->codec_id == CODEC_ID_H264 && avctx->bits_per_raw_sample > 8;
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// Common optimizations whether AltiVec is available or not
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c->prefetch = prefetch_ppc;
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if (!h264_high_depth) {
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switch (check_dcbzl_effect()) {
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case 32:
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c->clear_blocks = clear_blocks_dcbz32_ppc;
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break;
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case 128:
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c->clear_blocks = clear_blocks_dcbz128_ppc;
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break;
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default:
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break;
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}
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}
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#if HAVE_ALTIVEC
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if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx);
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if (av_get_cpu_flags() & AV_CPU_FLAG_ALTIVEC) {
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dsputil_init_altivec(c, avctx);
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float_init_altivec(c, avctx);
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int_init_altivec(c, avctx);
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c->gmc1 = gmc1_altivec;
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#if CONFIG_ENCODERS
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if (avctx->dct_algo == FF_DCT_AUTO ||
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avctx->dct_algo == FF_DCT_ALTIVEC) {
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c->fdct = fdct_altivec;
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}
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#endif //CONFIG_ENCODERS
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if (avctx->lowres==0) {
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if ((avctx->idct_algo == FF_IDCT_AUTO) ||
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(avctx->idct_algo == FF_IDCT_ALTIVEC)) {
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c->idct_put = idct_put_altivec;
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c->idct_add = idct_add_altivec;
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c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
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}else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) &&
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avctx->idct_algo==FF_IDCT_VP3){
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c->idct_put = ff_vp3_idct_put_altivec;
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c->idct_add = ff_vp3_idct_add_altivec;
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c->idct = ff_vp3_idct_altivec;
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c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
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}
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}
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}
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#endif /* HAVE_ALTIVEC */
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}
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