mirror of
https://github.com/FFmpeg/FFmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
182 lines
4.9 KiB
NASM
182 lines
4.9 KiB
NASM
;******************************************************************************
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;* optimized audio functions
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;* Copyright (c) 2008 Loren Merritt
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION .text
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; int ff_scalarproduct_int16(int16_t *v1, int16_t *v2, int order)
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INIT_XMM sse2
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cglobal scalarproduct_int16, 3,3,3, v1, v2, order
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add orderd, orderd
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add v1q, orderq
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add v2q, orderq
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neg orderq
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pxor m2, m2
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.loop:
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movu m0, [v1q + orderq]
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movu m1, [v1q + orderq + mmsize]
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pmaddwd m0, [v2q + orderq]
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pmaddwd m1, [v2q + orderq + mmsize]
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paddd m2, m0
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paddd m2, m1
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add orderq, mmsize*2
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jl .loop
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HADDD m2, m0
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movd eax, m2
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RET
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal scalarproduct_int16, 3,3,2, v1, v2, order
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add orderd, orderd
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add v1q, orderq
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add v2q, orderq
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neg orderq
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pxor m1, m1
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.loop:
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movu m0, [v1q + orderq]
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pmaddwd m0, [v2q + orderq]
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paddd m1, m0
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add orderq, mmsize
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jl .loop
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HADDD m1, m0
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movd eax, xm1
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RET
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%endif
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;-----------------------------------------------------------------------------
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; void ff_vector_clip_int32(int32_t *dst, const int32_t *src, int32_t min,
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; int32_t max, unsigned int len)
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;-----------------------------------------------------------------------------
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; %1 = number of xmm registers used
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; %2 = number of inline load/process/store loops per asm loop
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; %3 = process 4*mmsize (%3=0) or 8*mmsize (%3=1) bytes per loop
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; %4 = CLIPD function takes min/max as float instead of int (SSE2 version)
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; %5 = suffix
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%macro VECTOR_CLIP_INT32 4-5
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cglobal vector_clip_int32%5, 5,5,%1, dst, src, min, max, len
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%if %4
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cvtsi2ss m4, minm
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cvtsi2ss m5, maxm
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%else
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movd m4, minm
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movd m5, maxm
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%endif
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SPLATD m4
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SPLATD m5
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.loop:
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%assign %%i 0
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%rep %2
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mova m0, [srcq + mmsize * (0 + %%i)]
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mova m1, [srcq + mmsize * (1 + %%i)]
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mova m2, [srcq + mmsize * (2 + %%i)]
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mova m3, [srcq + mmsize * (3 + %%i)]
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%if %3
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mova m7, [srcq + mmsize * (4 + %%i)]
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mova m8, [srcq + mmsize * (5 + %%i)]
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mova m9, [srcq + mmsize * (6 + %%i)]
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mova m10, [srcq + mmsize * (7 + %%i)]
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%endif
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CLIPD m0, m4, m5, m6
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CLIPD m1, m4, m5, m6
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CLIPD m2, m4, m5, m6
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CLIPD m3, m4, m5, m6
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%if %3
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CLIPD m7, m4, m5, m6
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CLIPD m8, m4, m5, m6
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CLIPD m9, m4, m5, m6
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CLIPD m10, m4, m5, m6
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%endif
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mova [dstq + mmsize * (0 + %%i)], m0
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mova [dstq + mmsize * (1 + %%i)], m1
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mova [dstq + mmsize * (2 + %%i)], m2
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mova [dstq + mmsize * (3 + %%i)], m3
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%if %3
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mova [dstq + mmsize * (4 + %%i)], m7
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mova [dstq + mmsize * (5 + %%i)], m8
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mova [dstq + mmsize * (6 + %%i)], m9
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mova [dstq + mmsize * (7 + %%i)], m10
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%endif
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%assign %%i (%%i + 4 * (1 + %3))
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%endrep
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add srcq, mmsize*4*(%2+%3)
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add dstq, mmsize*4*(%2+%3)
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sub lend, mmsize*(%2+%3)
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jg .loop
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RET
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%endmacro
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INIT_XMM sse2
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VECTOR_CLIP_INT32 6, 1, 0, 0, _int
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VECTOR_CLIP_INT32 6, 2, 0, 1
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INIT_XMM sse4
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%ifdef m8
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VECTOR_CLIP_INT32 11, 1, 1, 0
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%else
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VECTOR_CLIP_INT32 6, 1, 0, 0
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%endif
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; void ff_vector_clipf_sse(float *dst, const float *src,
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; int len, float min, float max)
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INIT_XMM sse
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cglobal vector_clipf, 3, 3, 6, dst, src, len, min, max
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%if ARCH_X86_32
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VBROADCASTSS m0, minm
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VBROADCASTSS m1, maxm
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%elif WIN64
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SWAP 0, 3
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VBROADCASTSS m0, m0
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VBROADCASTSS m1, maxm
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%else ; 64bit sysv
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VBROADCASTSS m0, m0
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VBROADCASTSS m1, m1
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%endif
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movsxdifnidn lenq, lend
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.loop:
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mova m2, [srcq + 4 * lenq - 4 * mmsize]
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mova m3, [srcq + 4 * lenq - 3 * mmsize]
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mova m4, [srcq + 4 * lenq - 2 * mmsize]
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mova m5, [srcq + 4 * lenq - 1 * mmsize]
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maxps m2, m0
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maxps m3, m0
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maxps m4, m0
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maxps m5, m0
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minps m2, m1
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minps m3, m1
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minps m4, m1
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minps m5, m1
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mova [dstq + 4 * lenq - 4 * mmsize], m2
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mova [dstq + 4 * lenq - 3 * mmsize], m3
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mova [dstq + 4 * lenq - 2 * mmsize], m4
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mova [dstq + 4 * lenq - 1 * mmsize], m5
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sub lenq, mmsize
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jg .loop
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RET
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