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9b90d0d36a
C908: vsad_4_c: 681.0 vsad_4_rvv_i32: 182.2 vsad_5_c: 278.0 vsad_5_rvv_i32: 145.2 vsse_4_c: 595.0 vsse_4_rvv_i32: 125.2 vsse_5_c: 281.0 vsse_5_rvv_i32: 101.2 Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
410 lines
12 KiB
ArmAsm
410 lines
12 KiB
ArmAsm
/*
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* Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS).
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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.macro pix_abs_ret
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vsetivli zero, 1, e32, m1, ta, ma
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vmv.x.s a0, v0
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ret
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.endm
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func ff_pix_abs16_rvv, zve32x
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vsetivli zero, 1, e32, m1, ta, ma
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vmv.s.x v0, zero
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1:
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vsetivli zero, 16, e8, m1, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (a2)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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add a1, a1, a3
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vwsubu.vv v20, v12, v4
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vsetvli zero, zero, e16, m2, tu, ma
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vmax.vv v16, v16, v20
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add a2, a2, a3
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vwredsum.vs v0, v16, v0
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bnez a4, 1b
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pix_abs_ret
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endfunc
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func ff_pix_abs8_rvv, zve32x
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vsetivli zero, 1, e32, m1, ta, ma
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vmv.s.x v0, zero
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1:
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vsetivli zero, 8, e8, mf2, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (a2)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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add a1, a1, a3
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vwsubu.vv v20, v12, v4
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vsetvli zero, zero, e16, m1, tu, ma
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vmax.vv v16, v16, v20
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add a2, a2, a3
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vwredsum.vs v0, v16, v0
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bnez a4, 1b
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pix_abs_ret
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endfunc
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func ff_pix_abs16_x2_rvv, zve32x
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csrwi vxrm, 0
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vsetivli zero, 1, e32, m1, ta, ma
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li t5, 1
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vmv.s.x v0, zero
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1:
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vsetivli zero, 17, e8, m2, tu, ma
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vle8.v v12, (a2)
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addi a4, a4, -1
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vslide1down.vx v24, v12, t5
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vsetivli zero, 16, e8, m1, tu, ma
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vle8.v v4, (a1)
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vaaddu.vv v12, v12, v24
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vwsubu.vv v16, v4, v12
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add a1, a1, a3
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vwsubu.vv v20, v12, v4
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vsetvli zero, zero, e16, m2, tu, ma
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vmax.vv v16, v16, v20
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add a2, a2, a3
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vwredsum.vs v0, v16, v0
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bnez a4, 1b
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pix_abs_ret
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endfunc
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func ff_pix_abs8_x2_rvv, zve32x
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csrwi vxrm, 0
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vsetivli zero, 1, e32, m1, ta, ma
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li t5, 1
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vmv.s.x v0, zero
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1:
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vsetivli zero, 9, e8, m1, tu, ma
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vle8.v v12, (a2)
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addi a4, a4, -1
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vslide1down.vx v24, v12, t5
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vsetivli zero, 8, e8, mf2, tu, ma
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vle8.v v4, (a1)
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vaaddu.vv v12, v12, v24
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vwsubu.vv v16, v4, v12
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add a1, a1, a3
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vwsubu.vv v20, v12, v4
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vsetvli zero, zero, e16, m1, tu, ma
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vmax.vv v16, v16, v20
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add a2, a2, a3
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vwredsum.vs v0, v16, v0
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bnez a4, 1b
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pix_abs_ret
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endfunc
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func ff_pix_abs16_y2_rvv, zve32x
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csrwi vxrm, 0
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vsetivli zero, 1, e32, m1, ta, ma
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add t1, a2, a3
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vmv.s.x v0, zero
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1:
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vsetivli zero, 16, e8, m1, tu, ma
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vle8.v v12, (a2)
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vle8.v v24, (t1)
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addi a4, a4, -1
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vle8.v v4, (a1)
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vaaddu.vv v12, v12, v24
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vwsubu.vv v16, v4, v12
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vwsubu.vv v20, v12, v4
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add a1, a1, a3
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vsetvli zero, zero, e16, m2, tu, ma
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add a2, a2, a3
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vmax.vv v16, v16, v20
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add t1, t1, a3
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vwredsum.vs v0, v16, v0
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bnez a4, 1b
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pix_abs_ret
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endfunc
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func ff_pix_abs8_y2_rvv, zve32x
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csrwi vxrm, 0
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vsetivli zero, 1, e32, m1, ta, ma
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add t1, a2, a3
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vmv.s.x v0, zero
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1:
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vsetivli zero, 8, e8, mf2, tu, ma
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vle8.v v12, (a2)
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vle8.v v24, (t1)
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addi a4, a4, -1
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vle8.v v4, (a1)
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vaaddu.vv v12, v12, v24
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vwsubu.vv v16, v4, v12
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vwsubu.vv v20, v12, v4
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add a1, a1, a3
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vsetvli zero, zero, e16, m1, tu, ma
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add a2, a2, a3
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vmax.vv v16, v16, v20
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add t1, t1, a3
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vwredsum.vs v0, v16, v0
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bnez a4, 1b
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pix_abs_ret
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endfunc
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func ff_sse16_rvv, zve32x
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vsetivli t0, 16, e32, m4, ta, ma
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, m1, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (a2)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, m2, tu, ma
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vwmacc.vv v24, v16, v16
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add a1, a1, a3
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add a2, a2, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m4, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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endfunc
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func ff_sse8_rvv, zve32x
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vsetivli t0, 8, e32, m2, ta, ma
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, mf2, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (a2)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, m1, tu, ma
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vwmacc.vv v24, v16, v16
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add a1, a1, a3
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add a2, a2, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m2, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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endfunc
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func ff_sse4_rvv, zve32x
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vsetivli t0, 4, e32, m1, ta, ma
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, mf4, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (a2)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, mf2, tu, ma
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vwmacc.vv v24, v16, v16
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add a1, a1, a3
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add a2, a2, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m1, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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endfunc
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.macro vabsaddu dst src tmp
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vneg.v \tmp, \src
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vmax.vv \tmp, \src, \tmp
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vwaddu.wv \dst, \dst, \tmp
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.endm
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.macro vsad_vsse16 type
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vsetivli t0, 16, e32, m4, ta, ma
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addi a4, a4, -1
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add t1, a1, a3
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add t2, a2, a3
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, m1, tu, ma
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vle8.v v4, (a1)
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vle8.v v8, (t1)
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vle8.v v12, (a2)
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vle8.v v16, (t2)
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addi a4, a4, -1
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vwsubu.vv v28, v4, v12
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vwsubu.wv v12, v28, v8
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vwaddu.wv v28, v12, v16
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vsetvli zero, zero, e16, m2, tu, ma
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.ifc \type,abs
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vabsaddu v24, v28, v12
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.endif
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.ifc \type,square
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vwmacc.vv v24, v28, v28
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.endif
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add a1, a1, a3
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add a2, a2, a3
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add t1, t1, a3
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add t2, t2, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m4, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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.endm
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.macro vsad_vsse8 type
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vsetivli t0, 8, e32, m2, ta, ma
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addi a4, a4, -1
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add t1, a1, a3
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add t2, a2, a3
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, mf2, tu, ma
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vle8.v v4, (a1)
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vle8.v v8, (t1)
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vle8.v v12, (a2)
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vle8.v v16, (t2)
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addi a4, a4, -1
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vwsubu.vv v28, v4, v12
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vwsubu.wv v12, v28, v8
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vwaddu.wv v28, v12, v16
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vsetvli zero, zero, e16, m1, tu, ma
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.ifc \type,abs
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vabsaddu v24, v28, v12
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.endif
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.ifc \type,square
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vwmacc.vv v24, v28, v28
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.endif
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add a1, a1, a3
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add a2, a2, a3
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add t1, t1, a3
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add t2, t2, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m2, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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.endm
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.macro vsad_vsse_intra16 type
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vsetivli t0, 16, e32, m4, ta, ma
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addi a4, a4, -1
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add t1, a1, a3
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, m1, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (t1)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, m2, tu, ma
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.ifc \type,abs
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vabsaddu v24, v16, v12
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.endif
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.ifc \type,square
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vwmacc.vv v24, v16, v16
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.endif
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add a1, a1, a3
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add t1, t1, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m4, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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.endm
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.macro vsad_vsse_intra8 type
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vsetivli t0, 8, e32, m2, ta, ma
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addi a4, a4, -1
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add t1, a1, a3
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, mf2, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (t1)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, m1, tu, ma
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.ifc \type,abs
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vabsaddu v24, v16, v12
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.endif
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.ifc \type,square
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vwmacc.vv v24, v16, v16
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.endif
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add a1, a1, a3
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add t1, t1, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m2, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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.endm
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func ff_vsse16_rvv, zve32x
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vsad_vsse16 square
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endfunc
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func ff_vsse8_rvv, zve32x
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vsad_vsse8 square
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endfunc
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func ff_vsse_intra16_rvv, zve32x
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vsad_vsse_intra16 square
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endfunc
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func ff_vsse_intra8_rvv, zve32x
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vsad_vsse_intra8 square
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endfunc
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func ff_vsad16_rvv, zve32x
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vsad_vsse16 abs
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endfunc
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func ff_vsad8_rvv, zve32x
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vsad_vsse8 abs
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endfunc
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func ff_vsad_intra16_rvv, zve32x
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vsad_vsse_intra16 abs
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endfunc
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func ff_vsad_intra8_rvv, zve32x
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vsad_vsse_intra8 abs
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endfunc
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