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6319601343
This instruction, if aligned on a 4-byte boundary, defines a valid target
("landing pad") for an indirect call or jump. Since this instruction is a
HINT, it is safe to assemble even if not included in the target
instruction set architecture.
The necessary alignment is already provided by the `func` macro. However
this still lacks the ELF attribute to indicate that the zicfilp is supported
in simple mode. This is left for future work as the ELF specification is not
ratified as of yet.
This will also nonobviously require the assembler to support zicfilp,
insofar as the `tail` pseudo-instruction shall clobber T2 (instead of T1) as
its temporary register.
240 lines
6.6 KiB
ArmAsm
240 lines
6.6 KiB
ArmAsm
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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* Loosely based on earlier work copyrighted by Måns Rullgård, 2008.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined (__riscv_float_abi_soft)
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#define NOHWF
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#define NOHWD
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#define HWF #
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#define HWD #
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#elif defined (__riscv_float_abi_single)
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#define NOHWF #
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#define NOHWD
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#define HWF
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#define HWD #
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#else
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#define NOHWF #
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#define NOHWD #
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#define HWF
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#define HWD
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#endif
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.macro archadd ext=, more:vararg
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.ifnb \ext
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.ifc \ext, b
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# B was defined later, is known to fewer assemblers.
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archadd zba, zbb, zbs
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.else
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.option arch, +\ext
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.endif
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archadd \more
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.endif
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.endm
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.macro func sym, exts:vararg
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.text
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.option push
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archadd \exts
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.global \sym
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.hidden \sym
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.type \sym, %function
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.option push
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.option norvc
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.align 2
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\sym:
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.option pop
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.macro endfunc
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.size \sym, . - \sym
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.option pop
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.previous
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.purgem endfunc
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.endm
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.endm
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.macro const sym, align=3, relocate=0
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.if \relocate
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.pushsection .data.rel.ro
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.else
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.pushsection .rodata
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.endif
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.align \align
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\sym:
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.macro endconst
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.size \sym, . - \sym
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.popsection
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.purgem endconst
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.endm
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.endm
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#if !defined (__riscv_zicfilp)
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.macro lpad lpl
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auipc zero, \lpl
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.endm
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#endif
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#if defined (__riscv_v_elen)
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# define RV_V_ELEN __riscv_v_elen
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#else
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/* Run-time detection of the V extension implies ELEN >= 64. */
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# define RV_V_ELEN 64
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#endif
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#if RV_V_ELEN == 32
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# define VSEW_MAX 2
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#else
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# define VSEW_MAX 3
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#endif
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.macro parse_vtype ew, tp, mp
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.ifc \ew,e8
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.equ vsew, 0
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.else
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.ifc \ew,e16
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.equ vsew, 1
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.else
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.ifc \ew,e32
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.equ vsew, 2
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.else
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.ifc \ew,e64
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.equ vsew, 3
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.else
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.error "Unknown element width \ew"
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.endif
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.endif
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.endif
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.endif
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.ifc \tp,tu
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.equ tp, 0
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.else
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.ifc \tp,ta
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.equ tp, 1
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.else
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.error "Unknown tail policy \tp"
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.endif
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.endif
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.ifc \mp,mu
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.equ mp, 0
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.else
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.ifc \mp,ma
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.equ mp, 1
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.else
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.error "Unknown mask policy \mp"
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.endif
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.endif
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.endm
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/**
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* Gets the vector type with the smallest suitable LMUL value.
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* @param[out] rd vector type destination register
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* @param vl vector length constant
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* @param ew element width: e8, e16, e32 or e64
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* @param tp tail policy: tu or ta
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* @param mp mask policty: mu or ma
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*/
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.macro vtype_ivli rd, avl, ew, tp=tu, mp=mu
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.if \avl <= 1
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.equ log2vl, 0
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.elseif \avl <= 2
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.equ log2vl, 1
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.elseif \avl <= 4
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.equ log2vl, 2
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.elseif \avl <= 8
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.equ log2vl, 3
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.elseif \avl <= 16
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.equ log2vl, 4
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.elseif \avl <= 32
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.equ log2vl, 5
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.elseif \avl <= 64
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.equ log2vl, 6
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.elseif \avl <= 128
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.equ log2vl, 7
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.else
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.error "Vector length \avl out of range"
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.endif
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parse_vtype \ew, \tp, \mp
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csrr \rd, vlenb
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clz \rd, \rd
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addi \rd, \rd, log2vl + 1 + VSEW_MAX - __riscv_xlen
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max \rd, \rd, zero // VLMUL must be >= VSEW - VSEW_MAX
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.if vsew < VSEW_MAX
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addi \rd, \rd, vsew - VSEW_MAX
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andi \rd, \rd, 7
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.endif
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ori \rd, \rd, (vsew << 3) | (tp << 6) | (mp << 7)
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.endm
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/**
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* Gets the vector type with the smallest suitable LMUL value.
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* @param[out] rd vector type destination register
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* @param rs vector length source register
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* @param[out] tmp temporary register to be clobbered
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* @param ew element width: e8, e16, e32 or e64
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* @param tp tail policy: tu or ta
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* @param mp mask policty: mu or ma
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* @param addend optional addend for the vector length register
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*/
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.macro vtype_vli rd, rs, tmp, ew, tp=tu, mp=mu, addend=0
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parse_vtype \ew, \tp, \mp
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/*
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* The difference between the CLZ's notionally equals the VLMUL value
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* for 4-bit elements. But we want the value for SEW_MAX-bit elements.
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*/
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slli \tmp, \rs, 1 + VSEW_MAX
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.if \addend - 1
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addi \tmp, \tmp, \addend - 1
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.endif
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csrr \rd, vlenb
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clz \tmp, \tmp
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clz \rd, \rd
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sub \rd, \rd, \tmp
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max \rd, \rd, zero // VLMUL must be >= VSEW - VSEW_MAX
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.if vsew < VSEW_MAX
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addi \rd, \rd, vsew - VSEW_MAX
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andi \rd, \rd, 7
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.endif
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ori \rd, \rd, (vsew << 3) | (tp << 6) | (mp << 7)
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.endm
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/**
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* Widens a vector type.
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* @param[out] rd widened vector type destination register
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* @param rs vector type source register
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* @param n number of times to widen (once by default)
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*/
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.macro vwtypei rd, rs, n=1
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xori \rd, \rs, 4
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addi \rd, \rd, (\n) * 011
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xori \rd, \rd, 4
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.endm
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/**
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* Narrows a vector type.
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* @param[out] rd narrowed vector type destination register
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* @param rs vector type source register
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* @param n number of times to narrow (once by default)
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*/
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.macro vntypei rd, rs, n=1
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vwtypei \rd, \rs, -(\n)
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.endm
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