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e6303192c7
point coprocessor available in some ARM11 cores). Patch by Siarhei Siamashka % siarhei.siamashka@gmail.com % Original thread: date: Apr 20, 2008 5:41 PM subject: [FFmpeg-devel] [PATCH] Some ARM VFP optimizations (vector_fmul, vector_fmul_reverse, float_to_int16) Originally committed as revision 13128 to svn://svn.ffmpeg.org/ffmpeg/trunk
209 lines
8.2 KiB
C
209 lines
8.2 KiB
C
/*
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* Copyright (c) 2008 Siarhei Siamashka <ssvb@users.sourceforge.net>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavcodec/dsputil.h"
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/*
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* VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle
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* throughput for almost all the instructions (except for double precision
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* arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles
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* for arithmetic operations. Scheduling code to avoid pipeline stalls is very
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* important for performance. One more interesting feature is that VFP has
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* independent load/store and arithmetics pipelines, so it is possible to make
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* them work simultaneously and get more than 1 operation per cycle. Load/store
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* pipeline can process 2 single precision floating point values per cycle and
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* supports bulk loads and stores for large sets of registers. Arithmetic operations
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* can be done on vectors, which allows to keep the arithmetics pipeline busy,
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* while the processor may issue and execute other instructions. Detailed
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* optimization manuals can be found at http://www.arm.com
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*/
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/**
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* ARM VFP optimized implementation of 'vector_fmul_c' function.
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* Assume that len is a positive number and is multiple of 8
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*/
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static void vector_fmul_vfp(float *dst, const float *src, int len)
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{
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int tmp;
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asm volatile(
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"fmrx %[tmp], fpscr\n\t"
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"orr %[tmp], %[tmp], #(3 << 16)\n\t" /* set vector size to 4 */
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"fmxr fpscr, %[tmp]\n\t"
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"fldmias %[dst_r]!, {s0-s3}\n\t"
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"fldmias %[src]!, {s8-s11}\n\t"
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"fldmias %[dst_r]!, {s4-s7}\n\t"
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"fldmias %[src]!, {s12-s15}\n\t"
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"fmuls s8, s0, s8\n\t"
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"1:\n\t"
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"subs %[len], %[len], #16\n\t"
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"fmuls s12, s4, s12\n\t"
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"fldmiasge %[dst_r]!, {s16-s19}\n\t"
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"fldmiasge %[src]!, {s24-s27}\n\t"
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"fldmiasge %[dst_r]!, {s20-s23}\n\t"
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"fldmiasge %[src]!, {s28-s31}\n\t"
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"fmulsge s24, s16, s24\n\t"
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"fstmias %[dst_w]!, {s8-s11}\n\t"
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"fstmias %[dst_w]!, {s12-s15}\n\t"
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"fmulsge s28, s20, s28\n\t"
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"fldmiasgt %[dst_r]!, {s0-s3}\n\t"
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"fldmiasgt %[src]!, {s8-s11}\n\t"
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"fldmiasgt %[dst_r]!, {s4-s7}\n\t"
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"fldmiasgt %[src]!, {s12-s15}\n\t"
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"fmulsge s8, s0, s8\n\t"
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"fstmiasge %[dst_w]!, {s24-s27}\n\t"
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"fstmiasge %[dst_w]!, {s28-s31}\n\t"
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"bgt 1b\n\t"
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"bic %[tmp], %[tmp], #(7 << 16)\n\t" /* set vector size back to 1 */
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"fmxr fpscr, %[tmp]\n\t"
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: [dst_w] "+&r" (dst), [dst_r] "+&r" (dst), [src] "+&r" (src), [len] "+&r" (len), [tmp] "=&r" (tmp)
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:
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: "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
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"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
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"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
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"cc", "memory");
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}
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/**
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* ARM VFP optimized implementation of 'vector_fmul_reverse_c' function.
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* Assume that len is a positive number and is multiple of 8
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*/
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static void vector_fmul_reverse_vfp(float *dst, const float *src0, const float *src1, int len)
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{
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src1 += len;
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asm volatile(
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"fldmdbs %[src1]!, {s0-s3}\n\t"
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"fldmias %[src0]!, {s8-s11}\n\t"
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"fldmdbs %[src1]!, {s4-s7}\n\t"
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"fldmias %[src0]!, {s12-s15}\n\t"
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"fmuls s8, s3, s8\n\t"
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"fmuls s9, s2, s9\n\t"
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"fmuls s10, s1, s10\n\t"
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"fmuls s11, s0, s11\n\t"
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"1:\n\t"
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"subs %[len], %[len], #16\n\t"
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"fldmdbsge %[src1]!, {s16-s19}\n\t"
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"fmuls s12, s7, s12\n\t"
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"fldmiasge %[src0]!, {s24-s27}\n\t"
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"fmuls s13, s6, s13\n\t"
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"fldmdbsge %[src1]!, {s20-s23}\n\t"
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"fmuls s14, s5, s14\n\t"
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"fldmiasge %[src0]!, {s28-s31}\n\t"
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"fmuls s15, s4, s15\n\t"
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"fmulsge s24, s19, s24\n\t"
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"fldmdbsgt %[src1]!, {s0-s3}\n\t"
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"fmulsge s25, s18, s25\n\t"
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"fstmias %[dst]!, {s8-s13}\n\t"
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"fmulsge s26, s17, s26\n\t"
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"fldmiasgt %[src0]!, {s8-s11}\n\t"
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"fmulsge s27, s16, s27\n\t"
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"fmulsge s28, s23, s28\n\t"
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"fldmdbsgt %[src1]!, {s4-s7}\n\t"
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"fmulsge s29, s22, s29\n\t"
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"fstmias %[dst]!, {s14-s15}\n\t"
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"fmulsge s30, s21, s30\n\t"
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"fmulsge s31, s20, s31\n\t"
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"fmulsge s8, s3, s8\n\t"
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"fldmiasgt %[src0]!, {s12-s15}\n\t"
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"fmulsge s9, s2, s9\n\t"
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"fmulsge s10, s1, s10\n\t"
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"fstmiasge %[dst]!, {s24-s27}\n\t"
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"fmulsge s11, s0, s11\n\t"
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"fstmiasge %[dst]!, {s28-s31}\n\t"
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"bgt 1b\n\t"
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: [dst] "+&r" (dst), [src0] "+&r" (src0), [src1] "+&r" (src1), [len] "+&r" (len)
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:
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: "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
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"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
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"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
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"cc", "memory");
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}
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#ifdef HAVE_ARMV6
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/**
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* ARM VFP optimized float to int16 conversion.
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* Assume that len is a positive number and is multiple of 8, destination
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* buffer is at least 4 bytes aligned (8 bytes alignment is better for
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* performance), little endian byte sex
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*/
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void float_to_int16_vfp(int16_t *dst, const float *src, int len)
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{
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asm volatile(
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"fldmias %[src]!, {s16-s23}\n\t"
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"ftosis s0, s16\n\t"
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"ftosis s1, s17\n\t"
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"ftosis s2, s18\n\t"
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"ftosis s3, s19\n\t"
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"ftosis s4, s20\n\t"
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"ftosis s5, s21\n\t"
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"ftosis s6, s22\n\t"
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"ftosis s7, s23\n\t"
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"1:\n\t"
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"subs %[len], %[len], #8\n\t"
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"fmrrs r3, r4, {s0, s1}\n\t"
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"fmrrs r5, r6, {s2, s3}\n\t"
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"fmrrs r7, r8, {s4, s5}\n\t"
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"fmrrs ip, lr, {s6, s7}\n\t"
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"fldmiasgt %[src]!, {s16-s23}\n\t"
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"ssat r4, #16, r4\n\t"
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"ssat r3, #16, r3\n\t"
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"ssat r6, #16, r6\n\t"
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"ssat r5, #16, r5\n\t"
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"pkhbt r3, r3, r4, lsl #16\n\t"
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"pkhbt r4, r5, r6, lsl #16\n\t"
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"ftosisgt s0, s16\n\t"
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"ftosisgt s1, s17\n\t"
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"ftosisgt s2, s18\n\t"
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"ftosisgt s3, s19\n\t"
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"ftosisgt s4, s20\n\t"
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"ftosisgt s5, s21\n\t"
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"ftosisgt s6, s22\n\t"
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"ftosisgt s7, s23\n\t"
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"ssat r8, #16, r8\n\t"
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"ssat r7, #16, r7\n\t"
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"ssat lr, #16, lr\n\t"
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"ssat ip, #16, ip\n\t"
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"pkhbt r5, r7, r8, lsl #16\n\t"
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"pkhbt r6, ip, lr, lsl #16\n\t"
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"stmia %[dst]!, {r3-r6}\n\t"
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"bgt 1b\n\t"
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: [dst] "+&r" (dst), [src] "+&r" (src), [len] "+&r" (len)
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:
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: "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
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"r3", "r4", "r5", "r6", "r7", "r8", "ip", "lr",
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"cc", "memory");
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}
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#endif
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void ff_float_init_arm_vfp(DSPContext* c, AVCodecContext *avctx)
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{
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c->vector_fmul = vector_fmul_vfp;
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c->vector_fmul_reverse = vector_fmul_reverse_vfp;
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#ifdef HAVE_ARMV6
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c->float_to_int16 = float_to_int16_vfp;
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#endif
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}
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