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89ec4adad6
1.MMI_ load/store macros are defined in libavutil/mips/mmiutils.h 2.Replace some unnecessary unaligned access with aligned operator 3.The MMI_ load/store is compatible with cpu loongson2e/2f which not support instructions start with gs Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
705 lines
38 KiB
C
705 lines
38 KiB
C
/*
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* Loongson SIMD optimized h264chroma
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*
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* Copyright (c) 2015 Loongson Technology Corporation Limited
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* Copyright (c) 2015 Zhou Xiaoyong <zhouxiaoyong@loongson.cn>
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* Zhang Shuangshuang <zhangshuangshuang@ict.ac.cn>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "h264chroma_mips.h"
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#include "constants.h"
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#include "libavutil/mips/mmiutils.h"
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void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
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int h, int x, int y)
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{
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const int A = (8 - x) * (8 - y);
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const int B = x * (8 - y);
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const int C = (8 - x) * y;
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const int D = x * y;
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const int E = B + C;
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double ftmp[10];
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uint64_t tmp[1];
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mips_reg addr[1];
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DECLARE_VAR_ALL64;
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if (D) {
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__asm__ volatile (
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"dli %[tmp0], 0x06 \n\t"
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"pshufh %[A], %[A], %[ftmp0] \n\t"
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"pshufh %[B], %[B], %[ftmp0] \n\t"
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"mtc1 %[tmp0], %[ftmp9] \n\t"
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"pshufh %[C], %[C], %[ftmp0] \n\t"
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"pshufh %[D], %[D], %[ftmp0] \n\t"
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"1: \n\t"
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PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
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MMI_ULDC1(%[ftmp1], %[src], 0x00)
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MMI_ULDC1(%[ftmp2], %[src], 0x01)
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MMI_ULDC1(%[ftmp3], %[addr0], 0x00)
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MMI_ULDC1(%[ftmp4], %[addr0], 0x01)
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"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp7], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp8], %[ftmp2], %[ftmp0] \n\t"
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"pmullh %[ftmp5], %[ftmp5], %[A] \n\t"
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"pmullh %[ftmp7], %[ftmp7], %[B] \n\t"
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"paddh %[ftmp1], %[ftmp5], %[ftmp7] \n\t"
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"pmullh %[ftmp6], %[ftmp6], %[A] \n\t"
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"pmullh %[ftmp8], %[ftmp8], %[B] \n\t"
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"paddh %[ftmp2], %[ftmp6], %[ftmp8] \n\t"
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"punpcklbh %[ftmp5], %[ftmp3], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp3], %[ftmp0] \n\t"
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"punpcklbh %[ftmp7], %[ftmp4], %[ftmp0] \n\t"
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"punpckhbh %[ftmp8], %[ftmp4], %[ftmp0] \n\t"
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"pmullh %[ftmp5], %[ftmp5], %[C] \n\t"
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"pmullh %[ftmp7], %[ftmp7], %[D] \n\t"
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"paddh %[ftmp3], %[ftmp5], %[ftmp7] \n\t"
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"pmullh %[ftmp6], %[ftmp6], %[C] \n\t"
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"pmullh %[ftmp8], %[ftmp8], %[D] \n\t"
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"paddh %[ftmp4], %[ftmp6], %[ftmp8] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
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"psrlh %[ftmp1], %[ftmp1], %[ftmp9] \n\t"
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"psrlh %[ftmp2], %[ftmp2], %[ftmp9] \n\t"
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"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
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"addi %[h], %[h], -0x01 \n\t"
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MMI_SDC1(%[ftmp1], %[dst], 0x00)
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PTR_ADDU "%[src], %[src], %[stride] \n\t"
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PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
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"bnez %[h], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
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[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
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[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
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[tmp0]"=&r"(tmp[0]),
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RESTRICT_ASM_ALL64
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[addr0]"=&r"(addr[0]),
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[dst]"+&r"(dst), [src]"+&r"(src),
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[h]"+&r"(h)
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: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
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[A]"f"(A), [B]"f"(B),
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[C]"f"(C), [D]"f"(D)
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: "memory"
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);
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} else if (E) {
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const int step = C ? stride : 1;
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__asm__ volatile (
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"dli %[tmp0], 0x06 \n\t"
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"pshufh %[A], %[A], %[ftmp0] \n\t"
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"pshufh %[E], %[E], %[ftmp0] \n\t"
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"mtc1 %[tmp0], %[ftmp7] \n\t"
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"1: \n\t"
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PTR_ADDU "%[addr0], %[src], %[step] \n\t"
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MMI_ULDC1(%[ftmp1], %[src], 0x00)
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MMI_ULDC1(%[ftmp2], %[addr0], 0x00)
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"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
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"pmullh %[ftmp3], %[ftmp3], %[A] \n\t"
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"pmullh %[ftmp5], %[ftmp5], %[E] \n\t"
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"paddh %[ftmp1], %[ftmp3], %[ftmp5] \n\t"
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"pmullh %[ftmp4], %[ftmp4], %[A] \n\t"
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"pmullh %[ftmp6], %[ftmp6], %[E] \n\t"
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"paddh %[ftmp2], %[ftmp4], %[ftmp6] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
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"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
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"psrlh %[ftmp2], %[ftmp2], %[ftmp7] \n\t"
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"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
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"addi %[h], %[h], -0x01 \n\t"
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MMI_SDC1(%[ftmp1], %[dst], 0x00)
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PTR_ADDU "%[src], %[src], %[stride] \n\t"
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PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
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"bnez %[h], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
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[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
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[tmp0]"=&r"(tmp[0]),
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RESTRICT_ASM_ALL64
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[addr0]"=&r"(addr[0]),
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[dst]"+&r"(dst), [src]"+&r"(src),
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[h]"+&r"(h)
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: [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step),
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[ff_pw_32]"f"(ff_pw_32),
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[A]"f"(A), [E]"f"(E)
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: "memory"
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);
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} else {
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__asm__ volatile (
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"dli %[tmp0], 0x06 \n\t"
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"pshufh %[A], %[A], %[ftmp0] \n\t"
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"mtc1 %[tmp0], %[ftmp4] \n\t"
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"1: \n\t"
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MMI_ULDC1(%[ftmp1], %[src], 0x00)
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"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
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"pmullh %[ftmp2], %[ftmp3], %[A] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
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"psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
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"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
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PTR_ADDU "%[src], %[src], %[stride] \n\t"
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MMI_SDC1(%[ftmp1], %[dst], 0x00)
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PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
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MMI_ULDC1(%[ftmp1], %[src], 0x00)
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"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
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"pmullh %[ftmp2], %[ftmp3], %[A] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
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"psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
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"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
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"addi %[h], %[h], -0x02 \n\t"
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MMI_SDC1(%[ftmp1], %[dst], 0x00)
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PTR_ADDU "%[src], %[src], %[stride] \n\t"
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PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
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"bnez %[h], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]),
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[tmp0]"=&r"(tmp[0]),
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RESTRICT_ASM_ALL64
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[dst]"+&r"(dst), [src]"+&r"(src),
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[h]"+&r"(h)
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: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
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[A]"f"(A)
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: "memory"
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);
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}
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}
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void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
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int h, int x, int y)
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{
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const int A = (8 - x) * (8 - y);
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const int B = x * (8 - y);
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const int C = (8 - x) * y;
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const int D = x * y;
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const int E = B + C;
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double ftmp[10];
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uint64_t tmp[1];
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mips_reg addr[1];
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DECLARE_VAR_ALL64;
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if (D) {
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__asm__ volatile (
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"dli %[tmp0], 0x06 \n\t"
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"pshufh %[A], %[A], %[ftmp0] \n\t"
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"pshufh %[B], %[B], %[ftmp0] \n\t"
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"mtc1 %[tmp0], %[ftmp9] \n\t"
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"pshufh %[C], %[C], %[ftmp0] \n\t"
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"pshufh %[D], %[D], %[ftmp0] \n\t"
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"1: \n\t"
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PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
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MMI_ULDC1(%[ftmp1], %[src], 0x00)
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MMI_ULDC1(%[ftmp2], %[src], 0x01)
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MMI_ULDC1(%[ftmp3], %[addr0], 0x00)
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MMI_ULDC1(%[ftmp4], %[addr0], 0x01)
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"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp7], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp8], %[ftmp2], %[ftmp0] \n\t"
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"pmullh %[ftmp5], %[ftmp5], %[A] \n\t"
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"pmullh %[ftmp7], %[ftmp7], %[B] \n\t"
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"paddh %[ftmp1], %[ftmp5], %[ftmp7] \n\t"
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"pmullh %[ftmp6], %[ftmp6], %[A] \n\t"
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"pmullh %[ftmp8], %[ftmp8], %[B] \n\t"
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"paddh %[ftmp2], %[ftmp6], %[ftmp8] \n\t"
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"punpcklbh %[ftmp5], %[ftmp3], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp3], %[ftmp0] \n\t"
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"punpcklbh %[ftmp7], %[ftmp4], %[ftmp0] \n\t"
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"punpckhbh %[ftmp8], %[ftmp4], %[ftmp0] \n\t"
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"pmullh %[ftmp5], %[ftmp5], %[C] \n\t"
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"pmullh %[ftmp7], %[ftmp7], %[D] \n\t"
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"paddh %[ftmp3], %[ftmp5], %[ftmp7] \n\t"
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"pmullh %[ftmp6], %[ftmp6], %[C] \n\t"
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"pmullh %[ftmp8], %[ftmp8], %[D] \n\t"
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"paddh %[ftmp4], %[ftmp6], %[ftmp8] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
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"psrlh %[ftmp1], %[ftmp1], %[ftmp9] \n\t"
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"psrlh %[ftmp2], %[ftmp2], %[ftmp9] \n\t"
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"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
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MMI_LDC1(%[ftmp2], %[dst], 0x00)
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"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
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"addi %[h], %[h], -0x01 \n\t"
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MMI_SDC1(%[ftmp1], %[dst], 0x00)
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PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
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PTR_ADDU "%[src], %[src], %[stride] \n\t"
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"bnez %[h], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
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[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
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[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
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[tmp0]"=&r"(tmp[0]),
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RESTRICT_ASM_ALL64
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[addr0]"=&r"(addr[0]),
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[dst]"+&r"(dst), [src]"+&r"(src),
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[h]"+&r"(h)
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: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
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[A]"f"(A), [B]"f"(B),
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[C]"f"(C), [D]"f"(D)
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: "memory"
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);
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} else if (E) {
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const int step = C ? stride : 1;
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__asm__ volatile (
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"dli %[tmp0], 0x06 \n\t"
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"pshufh %[A], %[A], %[ftmp0] \n\t"
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"pshufh %[E], %[E], %[ftmp0] \n\t"
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"mtc1 %[tmp0], %[ftmp7] \n\t"
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"1: \n\t"
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PTR_ADDU "%[addr0], %[src], %[step] \n\t"
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MMI_ULDC1(%[ftmp1], %[src], 0x00)
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MMI_ULDC1(%[ftmp2], %[addr0], 0x00)
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"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
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"pmullh %[ftmp3], %[ftmp3], %[A] \n\t"
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"pmullh %[ftmp5], %[ftmp5], %[E] \n\t"
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"paddh %[ftmp1], %[ftmp3], %[ftmp5] \n\t"
|
|
"pmullh %[ftmp4], %[ftmp4], %[A] \n\t"
|
|
"pmullh %[ftmp6], %[ftmp6], %[E] \n\t"
|
|
"paddh %[ftmp2], %[ftmp4], %[ftmp6] \n\t"
|
|
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
"psrlh %[ftmp2], %[ftmp2], %[ftmp7] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
MMI_LDC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"addi %[h], %[h], -0x01 \n\t"
|
|
MMI_SDC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_ALL64
|
|
[addr0]"=&r"(addr[0]),
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step),
|
|
[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A), [E]"f"(E)
|
|
: "memory"
|
|
);
|
|
} else {
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp4] \n\t"
|
|
|
|
"1: \n\t"
|
|
MMI_ULDC1(%[ftmp1], %[src], 0x00)
|
|
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
|
|
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
|
|
"pmullh %[ftmp2], %[ftmp3], %[A] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
|
|
"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
MMI_LDC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
MMI_SDC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
|
|
MMI_ULDC1(%[ftmp1], %[src], 0x00)
|
|
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
|
|
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
|
|
"pmullh %[ftmp2], %[ftmp3], %[A] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"paddh %[ftmp2], %[ftmp2], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
|
|
"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
MMI_LDC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"addi %[h], %[h], -0x02 \n\t"
|
|
MMI_SDC1(%[ftmp1], %[dst], 0x00)
|
|
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[ftmp4]"=&f"(ftmp[4]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_ALL64
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A)
|
|
: "memory"
|
|
);
|
|
}
|
|
}
|
|
|
|
void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
|
|
int h, int x, int y)
|
|
{
|
|
const int A = (8 - x) * (8 - y);
|
|
const int B = x * (8 - y);
|
|
const int C = (8 - x) * y;
|
|
const int D = x * y;
|
|
const int E = B + C;
|
|
double ftmp[8];
|
|
uint64_t tmp[1];
|
|
mips_reg addr[1];
|
|
DECLARE_VAR_LOW32;
|
|
|
|
if (D) {
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"pshufh %[B], %[B], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp7] \n\t"
|
|
"pshufh %[C], %[C], %[ftmp0] \n\t"
|
|
"pshufh %[D], %[D], %[ftmp0] \n\t"
|
|
|
|
"1: \n\t"
|
|
PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
MMI_ULWC1(%[ftmp2], %[src], 0x01)
|
|
MMI_ULWC1(%[ftmp3], %[addr0], 0x00)
|
|
MMI_ULWC1(%[ftmp4], %[addr0], 0x01)
|
|
|
|
"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
|
|
"punpcklbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp5], %[ftmp5], %[A] \n\t"
|
|
"pmullh %[ftmp6], %[ftmp6], %[B] \n\t"
|
|
"paddh %[ftmp1], %[ftmp5], %[ftmp6] \n\t"
|
|
|
|
"punpcklbh %[ftmp5], %[ftmp3], %[ftmp0] \n\t"
|
|
"punpcklbh %[ftmp6], %[ftmp4], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp5], %[ftmp5], %[C] \n\t"
|
|
"pmullh %[ftmp6], %[ftmp6], %[D] \n\t"
|
|
"paddh %[ftmp2], %[ftmp5], %[ftmp6] \n\t"
|
|
|
|
"paddh %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
"addi %[h], %[h], -0x01 \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_LOW32
|
|
[addr0]"=&r"(addr[0]),
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A), [B]"f"(B),
|
|
[C]"f"(C), [D]"f"(D)
|
|
: "memory"
|
|
);
|
|
} else if (E) {
|
|
const int step = C ? stride : 1;
|
|
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"pshufh %[E], %[E], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp5] \n\t"
|
|
|
|
"1: \n\t"
|
|
PTR_ADDU "%[addr0], %[src], %[step] \n\t"
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
MMI_ULWC1(%[ftmp2], %[addr0], 0x00)
|
|
|
|
"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
|
|
"punpcklbh %[ftmp4], %[ftmp2], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp3], %[ftmp3], %[A] \n\t"
|
|
"pmullh %[ftmp4], %[ftmp4], %[E] \n\t"
|
|
"paddh %[ftmp1], %[ftmp3], %[ftmp4] \n\t"
|
|
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
"addi %[h], %[h], -0x01 \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_LOW32
|
|
[addr0]"=&r"(addr[0]),
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step),
|
|
[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A), [E]"f"(E)
|
|
: "memory"
|
|
);
|
|
} else {
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp3] \n\t"
|
|
|
|
"1: \n\t"
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
"addi %[h], %[h], -0x02 \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_LOW32
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A)
|
|
: "memory"
|
|
);
|
|
}
|
|
}
|
|
|
|
void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
|
|
int h, int x, int y)
|
|
{
|
|
const int A = (8 - x) *(8 - y);
|
|
const int B = x * (8 - y);
|
|
const int C = (8 - x) * y;
|
|
const int D = x * y;
|
|
const int E = B + C;
|
|
double ftmp[8];
|
|
uint64_t tmp[1];
|
|
mips_reg addr[1];
|
|
DECLARE_VAR_LOW32;
|
|
|
|
if (D) {
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"pshufh %[B], %[B], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp7] \n\t"
|
|
"pshufh %[C], %[C], %[ftmp0] \n\t"
|
|
"pshufh %[D], %[D], %[ftmp0] \n\t"
|
|
|
|
"1: \n\t"
|
|
PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
MMI_ULWC1(%[ftmp2], %[src], 0x01)
|
|
MMI_ULWC1(%[ftmp3], %[addr0], 0x00)
|
|
MMI_ULWC1(%[ftmp4], %[addr0], 0x01)
|
|
|
|
"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
|
|
"punpcklbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp5], %[ftmp5], %[A] \n\t"
|
|
"pmullh %[ftmp6], %[ftmp6], %[B] \n\t"
|
|
"paddh %[ftmp1], %[ftmp5], %[ftmp6] \n\t"
|
|
|
|
"punpcklbh %[ftmp5], %[ftmp3], %[ftmp0] \n\t"
|
|
"punpcklbh %[ftmp6], %[ftmp4], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp5], %[ftmp5], %[C] \n\t"
|
|
"pmullh %[ftmp6], %[ftmp6], %[D] \n\t"
|
|
"paddh %[ftmp2], %[ftmp5], %[ftmp6] \n\t"
|
|
|
|
"paddh %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
MMI_LWC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"addi %[h], %[h], -0x01 \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_LOW32
|
|
[addr0]"=&r"(addr[0]),
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A), [B]"f"(B),
|
|
[C]"f"(C), [D]"f"(D)
|
|
: "memory"
|
|
);
|
|
} else if (E) {
|
|
const int step = C ? stride : 1;
|
|
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"pshufh %[E], %[E], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp5] \n\t"
|
|
"1: \n\t"
|
|
PTR_ADDU "%[addr0], %[src], %[step] \n\t"
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
MMI_ULWC1(%[ftmp2], %[addr0], 0x00)
|
|
|
|
"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
|
|
"punpcklbh %[ftmp4], %[ftmp2], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp3], %[ftmp3], %[A] \n\t"
|
|
"pmullh %[ftmp4], %[ftmp4], %[E] \n\t"
|
|
"paddh %[ftmp1], %[ftmp3], %[ftmp4] \n\t"
|
|
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
MMI_LWC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"addi %[h], %[h], -0x01 \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_LOW32
|
|
[addr0]"=&r"(addr[0]),
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step),
|
|
[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A), [E]"f"(E)
|
|
: "memory"
|
|
);
|
|
} else {
|
|
__asm__ volatile (
|
|
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
"dli %[tmp0], 0x06 \n\t"
|
|
"pshufh %[A], %[A], %[ftmp0] \n\t"
|
|
"mtc1 %[tmp0], %[ftmp3] \n\t"
|
|
|
|
"1: \n\t"
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
MMI_LWC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
|
|
MMI_ULWC1(%[ftmp1], %[src], 0x00)
|
|
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
|
|
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
|
|
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
|
|
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
|
|
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
MMI_LWC1(%[ftmp2], %[dst], 0x00)
|
|
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
"addi %[h], %[h], -0x02 \n\t"
|
|
MMI_SWC1(%[ftmp1], %[dst], 0x00)
|
|
|
|
PTR_ADDU "%[src], %[src], %[stride] \n\t"
|
|
PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
|
|
"bnez %[h], 1b \n\t"
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
[tmp0]"=&r"(tmp[0]),
|
|
RESTRICT_ASM_LOW32
|
|
[dst]"+&r"(dst), [src]"+&r"(src),
|
|
[h]"+&r"(h)
|
|
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
|
|
[A]"f"(A)
|
|
: "memory"
|
|
);
|
|
}
|
|
}
|