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44699db6db
Clang report following error in aacsbr_mips.c,ac3dsp_mips.c and aacdec_mips.c: "couldn't allocate output register for constraint 'r'" Use 'f' constraint for float variable. Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
624 lines
27 KiB
C
624 lines
27 KiB
C
/*
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* Copyright (c) 2012
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* MIPS Technologies, Inc., California.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Authors: Djordje Pesut (djordje@mips.com)
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* Mirjana Vulin (mvulin@mips.com)
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file
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* Reference: libavcodec/aacsbr.c
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*/
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#include "libavcodec/aac.h"
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#include "libavcodec/aacsbr.h"
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#include "libavutil/mips/asmdefs.h"
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#define ENVELOPE_ADJUSTMENT_OFFSET 2
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#if HAVE_INLINE_ASM
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#if HAVE_MIPSFPU
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static int sbr_lf_gen_mips(AACContext *ac, SpectralBandReplication *sbr,
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float X_low[32][40][2], const float W[2][32][32][2],
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int buf_idx)
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{
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int i, k;
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int temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
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float *p_x_low = &X_low[0][8][0];
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float *p_w = (float*)&W[buf_idx][0][0][0];
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float *p_x1_low = &X_low[0][0][0];
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float *p_w1 = (float*)&W[1-buf_idx][24][0][0];
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float *loop_end=p_x1_low + 2560;
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/* loop unrolled 8 times */
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__asm__ volatile (
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"1: \n\t"
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"sw $0, 0(%[p_x1_low]) \n\t"
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"sw $0, 4(%[p_x1_low]) \n\t"
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"sw $0, 8(%[p_x1_low]) \n\t"
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"sw $0, 12(%[p_x1_low]) \n\t"
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"sw $0, 16(%[p_x1_low]) \n\t"
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"sw $0, 20(%[p_x1_low]) \n\t"
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"sw $0, 24(%[p_x1_low]) \n\t"
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"sw $0, 28(%[p_x1_low]) \n\t"
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PTR_ADDIU "%[p_x1_low],%[p_x1_low], 32 \n\t"
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"bne %[p_x1_low], %[loop_end], 1b \n\t"
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PTR_ADDIU "%[p_x1_low],%[p_x1_low], -10240 \n\t"
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: [p_x1_low]"+r"(p_x1_low)
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: [loop_end]"r"(loop_end)
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: "memory"
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);
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for (k = 0; k < sbr->kx[1]; k++) {
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for (i = 0; i < 32; i+=4) {
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/* loop unrolled 4 times */
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__asm__ volatile (
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"lw %[temp0], 0(%[p_w]) \n\t"
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"lw %[temp1], 4(%[p_w]) \n\t"
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"lw %[temp2], 256(%[p_w]) \n\t"
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"lw %[temp3], 260(%[p_w]) \n\t"
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"lw %[temp4], 512(%[p_w]) \n\t"
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"lw %[temp5], 516(%[p_w]) \n\t"
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"lw %[temp6], 768(%[p_w]) \n\t"
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"lw %[temp7], 772(%[p_w]) \n\t"
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"sw %[temp0], 0(%[p_x_low]) \n\t"
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"sw %[temp1], 4(%[p_x_low]) \n\t"
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"sw %[temp2], 8(%[p_x_low]) \n\t"
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"sw %[temp3], 12(%[p_x_low]) \n\t"
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"sw %[temp4], 16(%[p_x_low]) \n\t"
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"sw %[temp5], 20(%[p_x_low]) \n\t"
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"sw %[temp6], 24(%[p_x_low]) \n\t"
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"sw %[temp7], 28(%[p_x_low]) \n\t"
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PTR_ADDIU "%[p_x_low], %[p_x_low], 32 \n\t"
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PTR_ADDIU "%[p_w], %[p_w], 1024 \n\t"
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: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1),
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[temp2]"=&r"(temp2), [temp3]"=&r"(temp3),
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[temp4]"=&r"(temp4), [temp5]"=&r"(temp5),
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[temp6]"=&r"(temp6), [temp7]"=&r"(temp7),
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[p_w]"+r"(p_w), [p_x_low]"+r"(p_x_low)
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:
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: "memory"
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);
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}
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p_x_low += 16;
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p_w -= 2046;
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}
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for (k = 0; k < sbr->kx[0]; k++) {
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for (i = 0; i < 2; i++) {
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/* loop unrolled 4 times */
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__asm__ volatile (
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"lw %[temp0], 0(%[p_w1]) \n\t"
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"lw %[temp1], 4(%[p_w1]) \n\t"
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"lw %[temp2], 256(%[p_w1]) \n\t"
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"lw %[temp3], 260(%[p_w1]) \n\t"
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"lw %[temp4], 512(%[p_w1]) \n\t"
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"lw %[temp5], 516(%[p_w1]) \n\t"
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"lw %[temp6], 768(%[p_w1]) \n\t"
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"lw %[temp7], 772(%[p_w1]) \n\t"
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"sw %[temp0], 0(%[p_x1_low]) \n\t"
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"sw %[temp1], 4(%[p_x1_low]) \n\t"
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"sw %[temp2], 8(%[p_x1_low]) \n\t"
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"sw %[temp3], 12(%[p_x1_low]) \n\t"
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"sw %[temp4], 16(%[p_x1_low]) \n\t"
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"sw %[temp5], 20(%[p_x1_low]) \n\t"
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"sw %[temp6], 24(%[p_x1_low]) \n\t"
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"sw %[temp7], 28(%[p_x1_low]) \n\t"
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PTR_ADDIU "%[p_x1_low], %[p_x1_low], 32 \n\t"
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PTR_ADDIU "%[p_w1], %[p_w1], 1024 \n\t"
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: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1),
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[temp2]"=&r"(temp2), [temp3]"=&r"(temp3),
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[temp4]"=&r"(temp4), [temp5]"=&r"(temp5),
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[temp6]"=&r"(temp6), [temp7]"=&r"(temp7),
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[p_w1]"+r"(p_w1), [p_x1_low]"+r"(p_x1_low)
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:
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: "memory"
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);
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}
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p_x1_low += 64;
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p_w1 -= 510;
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}
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return 0;
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}
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static int sbr_x_gen_mips(SpectralBandReplication *sbr, float X[2][38][64],
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const float Y0[38][64][2], const float Y1[38][64][2],
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const float X_low[32][40][2], int ch)
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{
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int k, i;
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const int i_f = 32;
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int temp0, temp1, temp2, temp3;
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const float *X_low1, *Y01, *Y11;
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float *x1=&X[0][0][0];
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float *j=x1+4864;
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const int i_Temp = FFMAX(2*sbr->data[ch].t_env_num_env_old - i_f, 0);
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/* loop unrolled 8 times */
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__asm__ volatile (
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"1: \n\t"
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"sw $0, 0(%[x1]) \n\t"
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"sw $0, 4(%[x1]) \n\t"
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"sw $0, 8(%[x1]) \n\t"
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"sw $0, 12(%[x1]) \n\t"
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"sw $0, 16(%[x1]) \n\t"
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"sw $0, 20(%[x1]) \n\t"
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"sw $0, 24(%[x1]) \n\t"
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"sw $0, 28(%[x1]) \n\t"
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PTR_ADDIU "%[x1],%[x1], 32 \n\t"
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"bne %[x1], %[j], 1b \n\t"
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PTR_ADDIU "%[x1],%[x1], -19456 \n\t"
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: [x1]"+r"(x1)
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: [j]"r"(j)
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: "memory"
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);
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if (i_Temp != 0) {
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X_low1=&X_low[0][2][0];
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for (k = 0; k < sbr->kx[0]; k++) {
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__asm__ volatile (
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"move %[i], $zero \n\t"
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"2: \n\t"
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"lw %[temp0], 0(%[X_low1]) \n\t"
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"lw %[temp1], 4(%[X_low1]) \n\t"
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"sw %[temp0], 0(%[x1]) \n\t"
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"sw %[temp1], 9728(%[x1]) \n\t"
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PTR_ADDIU "%[x1], %[x1], 256 \n\t"
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PTR_ADDIU "%[X_low1], %[X_low1], 8 \n\t"
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"addiu %[i], %[i], 1 \n\t"
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"bne %[i], %[i_Temp], 2b \n\t"
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: [x1]"+r"(x1), [X_low1]"+r"(X_low1), [i]"=&r"(i),
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[temp0]"=&r"(temp0), [temp1]"=&r"(temp1)
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: [i_Temp]"r"(i_Temp)
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: "memory"
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);
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x1-=(i_Temp<<6)-1;
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X_low1-=(i_Temp<<1)-80;
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}
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x1=&X[0][0][k];
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Y01=(float*)&Y0[32][k][0];
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for (; k < sbr->kx[0] + sbr->m[0]; k++) {
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__asm__ volatile (
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"move %[i], $zero \n\t"
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"3: \n\t"
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"lw %[temp0], 0(%[Y01]) \n\t"
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"lw %[temp1], 4(%[Y01]) \n\t"
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"sw %[temp0], 0(%[x1]) \n\t"
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"sw %[temp1], 9728(%[x1]) \n\t"
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PTR_ADDIU "%[x1], %[x1], 256 \n\t"
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PTR_ADDIU "%[Y01], %[Y01], 512 \n\t"
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"addiu %[i], %[i], 1 \n\t"
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"bne %[i], %[i_Temp], 3b \n\t"
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: [x1]"+r"(x1), [Y01]"+r"(Y01), [i]"=&r"(i),
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[temp0]"=&r"(temp0), [temp1]"=&r"(temp1)
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: [i_Temp]"r"(i_Temp)
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: "memory"
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);
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x1 -=(i_Temp<<6)-1;
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Y01 -=(i_Temp<<7)-2;
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}
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}
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x1=&X[0][i_Temp][0];
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X_low1=&X_low[0][i_Temp+2][0];
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temp3=38;
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for (k = 0; k < sbr->kx[1]; k++) {
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__asm__ volatile (
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"move %[i], %[i_Temp] \n\t"
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"4: \n\t"
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"lw %[temp0], 0(%[X_low1]) \n\t"
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"lw %[temp1], 4(%[X_low1]) \n\t"
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"sw %[temp0], 0(%[x1]) \n\t"
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"sw %[temp1], 9728(%[x1]) \n\t"
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PTR_ADDIU "%[x1], %[x1], 256 \n\t"
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PTR_ADDIU "%[X_low1],%[X_low1], 8 \n\t"
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"addiu %[i], %[i], 1 \n\t"
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"bne %[i], %[temp3], 4b \n\t"
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: [x1]"+r"(x1), [X_low1]"+r"(X_low1), [i]"=&r"(i),
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[temp0]"=&r"(temp0), [temp1]"=&r"(temp1),
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[temp2]"=&r"(temp2)
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: [i_Temp]"r"(i_Temp), [temp3]"r"(temp3)
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: "memory"
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);
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x1 -= ((38-i_Temp)<<6)-1;
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X_low1 -= ((38-i_Temp)<<1)- 80;
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}
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x1=&X[0][i_Temp][k];
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Y11=&Y1[i_Temp][k][0];
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temp2=32;
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for (; k < sbr->kx[1] + sbr->m[1]; k++) {
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__asm__ volatile (
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"move %[i], %[i_Temp] \n\t"
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"5: \n\t"
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"lw %[temp0], 0(%[Y11]) \n\t"
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"lw %[temp1], 4(%[Y11]) \n\t"
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"sw %[temp0], 0(%[x1]) \n\t"
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"sw %[temp1], 9728(%[x1]) \n\t"
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PTR_ADDIU "%[x1], %[x1], 256 \n\t"
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PTR_ADDIU "%[Y11], %[Y11], 512 \n\t"
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"addiu %[i], %[i], 1 \n\t"
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"bne %[i], %[temp2], 5b \n\t"
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: [x1]"+r"(x1), [Y11]"+r"(Y11), [i]"=&r"(i),
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[temp0]"=&r"(temp0), [temp1]"=&r"(temp1)
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: [i_Temp]"r"(i_Temp), [temp3]"r"(temp3),
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[temp2]"r"(temp2)
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: "memory"
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);
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x1 -= ((32-i_Temp)<<6)-1;
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Y11 -= ((32-i_Temp)<<7)-2;
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}
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return 0;
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}
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#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
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static void sbr_hf_assemble_mips(float Y1[38][64][2],
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const float X_high[64][40][2],
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SpectralBandReplication *sbr, SBRData *ch_data,
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const int e_a[2])
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{
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int e, i, j, m;
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const int h_SL = 4 * !sbr->bs_smoothing_mode;
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const int kx = sbr->kx[1];
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const int m_max = sbr->m[1];
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static const float h_smooth[5] = {
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0.33333333333333,
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0.30150283239582,
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0.21816949906249,
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0.11516383427084,
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0.03183050093751,
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};
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float (*g_temp)[48] = ch_data->g_temp, (*q_temp)[48] = ch_data->q_temp;
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int indexnoise = ch_data->f_indexnoise;
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int indexsine = ch_data->f_indexsine;
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float *g_temp1, *q_temp1, *pok, *pok1;
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uint32_t temp1, temp2, temp3, temp4;
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int size = m_max;
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if (sbr->reset) {
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for (i = 0; i < h_SL; i++) {
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memcpy(g_temp[i + 2*ch_data->t_env[0]], sbr->gain[0], m_max * sizeof(sbr->gain[0][0]));
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memcpy(q_temp[i + 2*ch_data->t_env[0]], sbr->q_m[0], m_max * sizeof(sbr->q_m[0][0]));
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}
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} else if (h_SL) {
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memcpy(g_temp[2*ch_data->t_env[0]], g_temp[2*ch_data->t_env_num_env_old], 4*sizeof(g_temp[0]));
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memcpy(q_temp[2*ch_data->t_env[0]], q_temp[2*ch_data->t_env_num_env_old], 4*sizeof(q_temp[0]));
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}
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for (e = 0; e < ch_data->bs_num_env; e++) {
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for (i = 2 * ch_data->t_env[e]; i < 2 * ch_data->t_env[e + 1]; i++) {
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g_temp1 = g_temp[h_SL + i];
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pok = sbr->gain[e];
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q_temp1 = q_temp[h_SL + i];
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pok1 = sbr->q_m[e];
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/* loop unrolled 4 times */
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for (j=0; j<(size>>2); j++) {
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__asm__ volatile (
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"lw %[temp1], 0(%[pok]) \n\t"
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"lw %[temp2], 4(%[pok]) \n\t"
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"lw %[temp3], 8(%[pok]) \n\t"
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"lw %[temp4], 12(%[pok]) \n\t"
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"sw %[temp1], 0(%[g_temp1]) \n\t"
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"sw %[temp2], 4(%[g_temp1]) \n\t"
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"sw %[temp3], 8(%[g_temp1]) \n\t"
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"sw %[temp4], 12(%[g_temp1]) \n\t"
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"lw %[temp1], 0(%[pok1]) \n\t"
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"lw %[temp2], 4(%[pok1]) \n\t"
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"lw %[temp3], 8(%[pok1]) \n\t"
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"lw %[temp4], 12(%[pok1]) \n\t"
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"sw %[temp1], 0(%[q_temp1]) \n\t"
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"sw %[temp2], 4(%[q_temp1]) \n\t"
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"sw %[temp3], 8(%[q_temp1]) \n\t"
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"sw %[temp4], 12(%[q_temp1]) \n\t"
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PTR_ADDIU "%[pok], %[pok], 16 \n\t"
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PTR_ADDIU "%[g_temp1], %[g_temp1], 16 \n\t"
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PTR_ADDIU "%[pok1], %[pok1], 16 \n\t"
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PTR_ADDIU "%[q_temp1], %[q_temp1], 16 \n\t"
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: [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),
|
|
[temp3]"=&r"(temp3), [temp4]"=&r"(temp4),
|
|
[pok]"+r"(pok), [g_temp1]"+r"(g_temp1),
|
|
[pok1]"+r"(pok1), [q_temp1]"+r"(q_temp1)
|
|
:
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
for (j=0; j<(size&3); j++) {
|
|
__asm__ volatile (
|
|
"lw %[temp1], 0(%[pok]) \n\t"
|
|
"lw %[temp2], 0(%[pok1]) \n\t"
|
|
"sw %[temp1], 0(%[g_temp1]) \n\t"
|
|
"sw %[temp2], 0(%[q_temp1]) \n\t"
|
|
PTR_ADDIU "%[pok], %[pok], 4 \n\t"
|
|
PTR_ADDIU "%[g_temp1], %[g_temp1], 4 \n\t"
|
|
PTR_ADDIU "%[pok1], %[pok1], 4 \n\t"
|
|
PTR_ADDIU "%[q_temp1], %[q_temp1], 4 \n\t"
|
|
|
|
: [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),
|
|
[temp3]"=&r"(temp3), [temp4]"=&r"(temp4),
|
|
[pok]"+r"(pok), [g_temp1]"+r"(g_temp1),
|
|
[pok1]"+r"(pok1), [q_temp1]"+r"(q_temp1)
|
|
:
|
|
: "memory"
|
|
);
|
|
}
|
|
}
|
|
}
|
|
|
|
for (e = 0; e < ch_data->bs_num_env; e++) {
|
|
for (i = 2 * ch_data->t_env[e]; i < 2 * ch_data->t_env[e + 1]; i++) {
|
|
LOCAL_ALIGNED_16(float, g_filt_tab, [48]);
|
|
LOCAL_ALIGNED_16(float, q_filt_tab, [48]);
|
|
float *g_filt, *q_filt;
|
|
|
|
if (h_SL && e != e_a[0] && e != e_a[1]) {
|
|
g_filt = g_filt_tab;
|
|
q_filt = q_filt_tab;
|
|
|
|
for (m = 0; m < m_max; m++) {
|
|
const int idx1 = i + h_SL;
|
|
g_filt[m] = 0.0f;
|
|
q_filt[m] = 0.0f;
|
|
|
|
for (j = 0; j <= h_SL; j++) {
|
|
g_filt[m] += g_temp[idx1 - j][m] * h_smooth[j];
|
|
q_filt[m] += q_temp[idx1 - j][m] * h_smooth[j];
|
|
}
|
|
}
|
|
} else {
|
|
g_filt = g_temp[i + h_SL];
|
|
q_filt = q_temp[i];
|
|
}
|
|
|
|
sbr->dsp.hf_g_filt(Y1[i] + kx, X_high + kx, g_filt, m_max,
|
|
i + ENVELOPE_ADJUSTMENT_OFFSET);
|
|
|
|
if (e != e_a[0] && e != e_a[1]) {
|
|
sbr->dsp.hf_apply_noise[indexsine](Y1[i] + kx, sbr->s_m[e],
|
|
q_filt, indexnoise,
|
|
kx, m_max);
|
|
} else {
|
|
int idx = indexsine&1;
|
|
int A = (1-((indexsine+(kx & 1))&2));
|
|
int B = (A^(-idx)) + idx;
|
|
float *out = &Y1[i][kx][idx];
|
|
float *in = sbr->s_m[e];
|
|
float temp0, temp1, temp2, temp3, temp4, temp5;
|
|
float A_f = (float)A;
|
|
float B_f = (float)B;
|
|
|
|
for (m = 0; m+1 < m_max; m+=2) {
|
|
|
|
temp2 = out[0];
|
|
temp3 = out[2];
|
|
|
|
__asm__ volatile(
|
|
"lwc1 %[temp0], 0(%[in]) \n\t"
|
|
"lwc1 %[temp1], 4(%[in]) \n\t"
|
|
"madd.s %[temp4], %[temp2], %[temp0], %[A_f] \n\t"
|
|
"madd.s %[temp5], %[temp3], %[temp1], %[B_f] \n\t"
|
|
"swc1 %[temp4], 0(%[out]) \n\t"
|
|
"swc1 %[temp5], 8(%[out]) \n\t"
|
|
PTR_ADDIU "%[in], %[in], 8 \n\t"
|
|
PTR_ADDIU "%[out], %[out], 16 \n\t"
|
|
|
|
: [temp0]"=&f" (temp0), [temp1]"=&f"(temp1),
|
|
[temp4]"=&f" (temp4), [temp5]"=&f"(temp5),
|
|
[in]"+r"(in), [out]"+r"(out)
|
|
: [A_f]"f"(A_f), [B_f]"f"(B_f), [temp2]"f"(temp2),
|
|
[temp3]"f"(temp3)
|
|
: "memory"
|
|
);
|
|
}
|
|
if(m_max&1)
|
|
out[2*m ] += in[m ] * A;
|
|
}
|
|
indexnoise = (indexnoise + m_max) & 0x1ff;
|
|
indexsine = (indexsine + 1) & 3;
|
|
}
|
|
}
|
|
ch_data->f_indexnoise = indexnoise;
|
|
ch_data->f_indexsine = indexsine;
|
|
}
|
|
|
|
static void sbr_hf_inverse_filter_mips(SBRDSPContext *dsp,
|
|
float (*alpha0)[2], float (*alpha1)[2],
|
|
const float X_low[32][40][2], int k0)
|
|
{
|
|
int k;
|
|
float temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7, c;
|
|
float *phi1, *alpha_1, *alpha_0, res1, res2, temp_real, temp_im;
|
|
|
|
c = 1.000001f;
|
|
|
|
for (k = 0; k < k0; k++) {
|
|
LOCAL_ALIGNED_16(float, phi, [3], [2][2]);
|
|
float dk;
|
|
phi1 = &phi[0][0][0];
|
|
alpha_1 = &alpha1[k][0];
|
|
alpha_0 = &alpha0[k][0];
|
|
dsp->autocorrelate(X_low[k], phi);
|
|
|
|
__asm__ volatile (
|
|
"lwc1 %[temp0], 40(%[phi1]) \n\t"
|
|
"lwc1 %[temp1], 16(%[phi1]) \n\t"
|
|
"lwc1 %[temp2], 24(%[phi1]) \n\t"
|
|
"lwc1 %[temp3], 28(%[phi1]) \n\t"
|
|
"mul.s %[dk], %[temp0], %[temp1] \n\t"
|
|
"lwc1 %[temp4], 0(%[phi1]) \n\t"
|
|
"mul.s %[res2], %[temp2], %[temp2] \n\t"
|
|
"lwc1 %[temp5], 4(%[phi1]) \n\t"
|
|
"madd.s %[res2], %[res2], %[temp3], %[temp3] \n\t"
|
|
"lwc1 %[temp6], 8(%[phi1]) \n\t"
|
|
"div.s %[res2], %[res2], %[c] \n\t"
|
|
"lwc1 %[temp0], 12(%[phi1]) \n\t"
|
|
"sub.s %[dk], %[dk], %[res2] \n\t"
|
|
|
|
: [temp0]"=&f"(temp0), [temp1]"=&f"(temp1), [temp2]"=&f"(temp2),
|
|
[temp3]"=&f"(temp3), [temp4]"=&f"(temp4), [temp5]"=&f"(temp5),
|
|
[temp6]"=&f"(temp6), [res2]"=&f"(res2), [dk]"=&f"(dk)
|
|
: [phi1]"r"(phi1), [c]"f"(c)
|
|
: "memory"
|
|
);
|
|
|
|
if (!dk) {
|
|
alpha_1[0] = 0;
|
|
alpha_1[1] = 0;
|
|
} else {
|
|
__asm__ volatile (
|
|
"mul.s %[temp_real], %[temp4], %[temp2] \n\t"
|
|
"nmsub.s %[temp_real], %[temp_real], %[temp5], %[temp3] \n\t"
|
|
"nmsub.s %[temp_real], %[temp_real], %[temp6], %[temp1] \n\t"
|
|
"mul.s %[temp_im], %[temp4], %[temp3] \n\t"
|
|
"madd.s %[temp_im], %[temp_im], %[temp5], %[temp2] \n\t"
|
|
"nmsub.s %[temp_im], %[temp_im], %[temp0], %[temp1] \n\t"
|
|
"div.s %[temp_real], %[temp_real], %[dk] \n\t"
|
|
"div.s %[temp_im], %[temp_im], %[dk] \n\t"
|
|
"swc1 %[temp_real], 0(%[alpha_1]) \n\t"
|
|
"swc1 %[temp_im], 4(%[alpha_1]) \n\t"
|
|
|
|
: [temp_real]"=&f" (temp_real), [temp_im]"=&f"(temp_im)
|
|
: [phi1]"r"(phi1), [temp0]"f"(temp0), [temp1]"f"(temp1),
|
|
[temp2]"f"(temp2), [temp3]"f"(temp3), [temp4]"f"(temp4),
|
|
[temp5]"f"(temp5), [temp6]"f"(temp6),
|
|
[alpha_1]"r"(alpha_1), [dk]"f"(dk)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
if (!phi1[4]) {
|
|
alpha_0[0] = 0;
|
|
alpha_0[1] = 0;
|
|
} else {
|
|
__asm__ volatile (
|
|
"lwc1 %[temp6], 0(%[alpha_1]) \n\t"
|
|
"lwc1 %[temp7], 4(%[alpha_1]) \n\t"
|
|
"mul.s %[temp_real], %[temp6], %[temp2] \n\t"
|
|
"add.s %[temp_real], %[temp_real], %[temp4] \n\t"
|
|
"madd.s %[temp_real], %[temp_real], %[temp7], %[temp3] \n\t"
|
|
"mul.s %[temp_im], %[temp7], %[temp2] \n\t"
|
|
"add.s %[temp_im], %[temp_im], %[temp5] \n\t"
|
|
"nmsub.s %[temp_im], %[temp_im], %[temp6], %[temp3] \n\t"
|
|
"div.s %[temp_real], %[temp_real], %[temp1] \n\t"
|
|
"div.s %[temp_im], %[temp_im], %[temp1] \n\t"
|
|
"neg.s %[temp_real], %[temp_real] \n\t"
|
|
"neg.s %[temp_im], %[temp_im] \n\t"
|
|
"swc1 %[temp_real], 0(%[alpha_0]) \n\t"
|
|
"swc1 %[temp_im], 4(%[alpha_0]) \n\t"
|
|
|
|
: [temp_real]"=&f"(temp_real), [temp_im]"=&f"(temp_im),
|
|
[temp6]"=&f"(temp6), [temp7]"=&f"(temp7),
|
|
[res1]"=&f"(res1), [res2]"=&f"(res2)
|
|
: [alpha_1]"r"(alpha_1), [alpha_0]"r"(alpha_0),
|
|
[temp0]"f"(temp0), [temp1]"f"(temp1), [temp2]"f"(temp2),
|
|
[temp3]"f"(temp3), [temp4]"f"(temp4), [temp5]"f"(temp5)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
__asm__ volatile (
|
|
"lwc1 %[temp1], 0(%[alpha_1]) \n\t"
|
|
"lwc1 %[temp2], 4(%[alpha_1]) \n\t"
|
|
"lwc1 %[temp_real], 0(%[alpha_0]) \n\t"
|
|
"lwc1 %[temp_im], 4(%[alpha_0]) \n\t"
|
|
"mul.s %[res1], %[temp1], %[temp1] \n\t"
|
|
"madd.s %[res1], %[res1], %[temp2], %[temp2] \n\t"
|
|
"mul.s %[res2], %[temp_real], %[temp_real] \n\t"
|
|
"madd.s %[res2], %[res2], %[temp_im], %[temp_im] \n\t"
|
|
|
|
: [temp_real]"=&f"(temp_real), [temp_im]"=&f"(temp_im),
|
|
[temp1]"=&f"(temp1), [temp2]"=&f"(temp2),
|
|
[res1]"=&f"(res1), [res2]"=&f"(res2)
|
|
: [alpha_1]"r"(alpha_1), [alpha_0]"r"(alpha_0)
|
|
: "memory"
|
|
);
|
|
|
|
if (res1 >= 16.0f || res2 >= 16.0f) {
|
|
alpha_1[0] = 0;
|
|
alpha_1[1] = 0;
|
|
alpha_0[0] = 0;
|
|
alpha_0[1] = 0;
|
|
}
|
|
}
|
|
}
|
|
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
|
|
#endif /* HAVE_MIPSFPU */
|
|
#endif /* HAVE_INLINE_ASM */
|
|
|
|
void ff_aacsbr_func_ptr_init_mips(AACSBRContext *c)
|
|
{
|
|
#if HAVE_INLINE_ASM
|
|
#if HAVE_MIPSFPU
|
|
c->sbr_lf_gen = sbr_lf_gen_mips;
|
|
c->sbr_x_gen = sbr_x_gen_mips;
|
|
#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
|
|
c->sbr_hf_inverse_filter = sbr_hf_inverse_filter_mips;
|
|
c->sbr_hf_assemble = sbr_hf_assemble_mips;
|
|
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
|
|
#endif /* HAVE_MIPSFPU */
|
|
#endif /* HAVE_INLINE_ASM */
|
|
}
|