mirror of
https://github.com/FFmpeg/FFmpeg.git
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16e65419ed
* commit 'f963f80399deb1a2b44c1bac3af7123e8a0c9e46': arm: Use .data.rel.ro for const data with relocations Conflicts: configure Merged-by: Michael Niedermayer <michaelni@gmx.at>
376 lines
15 KiB
ArmAsm
376 lines
15 KiB
ArmAsm
/*
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* ARM NEON optimised FFT
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*
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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* Copyright (c) 2009 Naotoshi Nojiri
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*
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* This algorithm (though not any of the implementation details) is
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* based on libdjbfft by D. J. Bernstein.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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#define M_SQRT1_2 0.70710678118654752440
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function fft4_neon
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vld1.32 {d0-d3}, [r0,:128]
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vext.32 q8, q1, q1, #1 @ i2,r3 d3=i3,r2
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vsub.f32 d6, d0, d1 @ r0-r1,i0-i1
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vsub.f32 d7, d16, d17 @ r3-r2,i2-i3
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vadd.f32 d4, d0, d1 @ r0+r1,i0+i1
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vadd.f32 d5, d2, d3 @ i2+i3,r2+r3
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vadd.f32 d1, d6, d7
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vsub.f32 d3, d6, d7
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vadd.f32 d0, d4, d5
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vsub.f32 d2, d4, d5
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vst1.32 {d0-d3}, [r0,:128]
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bx lr
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endfunc
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function fft8_neon
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mov r1, r0
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vld1.32 {d0-d3}, [r1,:128]!
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vld1.32 {d16-d19}, [r1,:128]
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movw r2, #0x04f3 @ sqrt(1/2)
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movt r2, #0x3f35
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eor r3, r2, #1<<31
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vdup.32 d31, r2
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vext.32 q11, q1, q1, #1 @ i2,r3,i3,r2
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vadd.f32 d4, d16, d17 @ r4+r5,i4+i5
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vmov d28, r3, r2
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vadd.f32 d5, d18, d19 @ r6+r7,i6+i7
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vsub.f32 d17, d16, d17 @ r4-r5,i4-i5
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vsub.f32 d19, d18, d19 @ r6-r7,i6-i7
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vrev64.32 d29, d28
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vadd.f32 d20, d0, d1 @ r0+r1,i0+i1
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vadd.f32 d21, d2, d3 @ r2+r3,i2+i3
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vmul.f32 d26, d17, d28 @ -a2r*w,a2i*w
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vext.32 q3, q2, q2, #1
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vmul.f32 d27, d19, d29 @ a3r*w,-a3i*w
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vsub.f32 d23, d22, d23 @ i2-i3,r3-r2
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vsub.f32 d22, d0, d1 @ r0-r1,i0-i1
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vmul.f32 d24, d17, d31 @ a2r*w,a2i*w
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vmul.f32 d25, d19, d31 @ a3r*w,a3i*w
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vadd.f32 d0, d20, d21
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vsub.f32 d2, d20, d21
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vadd.f32 d1, d22, d23
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vrev64.32 q13, q13
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vsub.f32 d3, d22, d23
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vsub.f32 d6, d6, d7
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vadd.f32 d24, d24, d26 @ a2r+a2i,a2i-a2r t1,t2
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vadd.f32 d25, d25, d27 @ a3r-a3i,a3i+a3r t5,t6
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vadd.f32 d7, d4, d5
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vsub.f32 d18, d2, d6
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vext.32 q13, q12, q12, #1
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vadd.f32 d2, d2, d6
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vsub.f32 d16, d0, d7
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vadd.f32 d5, d25, d24
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vsub.f32 d4, d26, d27
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vadd.f32 d0, d0, d7
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vsub.f32 d17, d1, d5
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vsub.f32 d19, d3, d4
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vadd.f32 d3, d3, d4
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vadd.f32 d1, d1, d5
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vst1.32 {d16-d19}, [r1,:128]
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vst1.32 {d0-d3}, [r0,:128]
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bx lr
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endfunc
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function fft16_neon
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movrel r1, mppm
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vld1.32 {d16-d19}, [r0,:128]! @ q8{r0,i0,r1,i1} q9{r2,i2,r3,i3}
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pld [r0, #32]
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vld1.32 {d2-d3}, [r1,:128]
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vext.32 q13, q9, q9, #1
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vld1.32 {d22-d25}, [r0,:128]! @ q11{r4,i4,r5,i5} q12{r6,i5,r7,i7}
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vadd.f32 d4, d16, d17
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vsub.f32 d5, d16, d17
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vadd.f32 d18, d18, d19
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vsub.f32 d19, d26, d27
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vadd.f32 d20, d22, d23
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vsub.f32 d22, d22, d23
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vsub.f32 d23, d24, d25
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vadd.f32 q8, q2, q9 @ {r0,i0,r1,i1}
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vadd.f32 d21, d24, d25
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vmul.f32 d24, d22, d2
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vsub.f32 q9, q2, q9 @ {r2,i2,r3,i3}
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vmul.f32 d25, d23, d3
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vuzp.32 d16, d17 @ {r0,r1,i0,i1}
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vmul.f32 q1, q11, d2[1]
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vuzp.32 d18, d19 @ {r2,r3,i2,i3}
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vrev64.32 q12, q12
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vadd.f32 q11, q12, q1 @ {t1a,t2a,t5,t6}
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vld1.32 {d24-d27}, [r0,:128]! @ q12{r8,i8,r9,i9} q13{r10,i10,r11,i11}
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vzip.32 q10, q11
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vld1.32 {d28-d31}, [r0,:128] @ q14{r12,i12,r13,i13} q15{r14,i14,r15,i15}
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vadd.f32 d0, d22, d20
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vadd.f32 d1, d21, d23
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vsub.f32 d2, d21, d23
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vsub.f32 d3, d22, d20
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sub r0, r0, #96
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vext.32 q13, q13, q13, #1
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vsub.f32 q10, q8, q0 @ {r4,r5,i4,i5}
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vadd.f32 q8, q8, q0 @ {r0,r1,i0,i1}
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vext.32 q15, q15, q15, #1
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vsub.f32 q11, q9, q1 @ {r6,r7,i6,i7}
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vswp d25, d26 @ q12{r8,i8,i10,r11} q13{r9,i9,i11,r10}
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vadd.f32 q9, q9, q1 @ {r2,r3,i2,i3}
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vswp d29, d30 @ q14{r12,i12,i14,r15} q15{r13,i13,i15,r14}
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vadd.f32 q0, q12, q13 @ {t1,t2,t5,t6}
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vadd.f32 q1, q14, q15 @ {t1a,t2a,t5a,t6a}
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movrelx r2, X(ff_cos_16)
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vsub.f32 q13, q12, q13 @ {t3,t4,t7,t8}
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vrev64.32 d1, d1
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vsub.f32 q15, q14, q15 @ {t3a,t4a,t7a,t8a}
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vrev64.32 d3, d3
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movrel r3, pmmp
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vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8}
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vswp d3, d30 @ q1{t1a,t2a,t3a,t4a} q15{t6a,t5a,t7a,t8a}
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vadd.f32 q12, q0, q13 @ {r8,i8,r9,i9}
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vadd.f32 q14, q1, q15 @ {r12,i12,r13,i13}
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vld1.32 {d4-d5}, [r2,:64]
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vsub.f32 q13, q0, q13 @ {r10,i10,r11,i11}
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vsub.f32 q15, q1, q15 @ {r14,i14,r15,i15}
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vswp d25, d28 @ q12{r8,i8,r12,i12} q14{r9,i9,r13,i13}
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vld1.32 {d6-d7}, [r3,:128]
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vrev64.32 q1, q14
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vmul.f32 q14, q14, d4[1]
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vmul.f32 q1, q1, q3
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vmla.f32 q14, q1, d5[1] @ {t1a,t2a,t5a,t6a}
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vswp d27, d30 @ q13{r10,i10,r14,i14} q15{r11,i11,r15,i15}
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vzip.32 q12, q14
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vadd.f32 d0, d28, d24
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vadd.f32 d1, d25, d29
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vsub.f32 d2, d25, d29
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vsub.f32 d3, d28, d24
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vsub.f32 q12, q8, q0 @ {r8,r9,i8,i9}
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vadd.f32 q8, q8, q0 @ {r0,r1,i0,i1}
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vsub.f32 q14, q10, q1 @ {r12,r13,i12,i13}
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mov r1, #32
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vadd.f32 q10, q10, q1 @ {r4,r5,i4,i5}
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vrev64.32 q0, q13
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vmul.f32 q13, q13, d5[0]
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vrev64.32 q1, q15
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vmul.f32 q15, q15, d5[1]
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vst2.32 {d16-d17},[r0,:128], r1
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vmul.f32 q0, q0, q3
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vst2.32 {d20-d21},[r0,:128], r1
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vmul.f32 q1, q1, q3
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vmla.f32 q13, q0, d5[0] @ {t1,t2,t5,t6}
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vmla.f32 q15, q1, d4[1] @ {t1a,t2a,t5a,t6a}
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vst2.32 {d24-d25},[r0,:128], r1
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vst2.32 {d28-d29},[r0,:128]
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vzip.32 q13, q15
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sub r0, r0, #80
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vadd.f32 d0, d30, d26
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vadd.f32 d1, d27, d31
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vsub.f32 d2, d27, d31
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vsub.f32 d3, d30, d26
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vsub.f32 q13, q9, q0 @ {r10,r11,i10,i11}
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vadd.f32 q9, q9, q0 @ {r2,r3,i2,i3}
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vsub.f32 q15, q11, q1 @ {r14,r15,i14,i15}
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vadd.f32 q11, q11, q1 @ {r6,r7,i6,i7}
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vst2.32 {d18-d19},[r0,:128], r1
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vst2.32 {d22-d23},[r0,:128], r1
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vst2.32 {d26-d27},[r0,:128], r1
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vst2.32 {d30-d31},[r0,:128]
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bx lr
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endfunc
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function fft_pass_neon
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push {r4-r6,lr}
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mov r6, r2 @ n
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lsl r5, r2, #3 @ 2 * n * sizeof FFTSample
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lsl r4, r2, #4 @ 2 * n * sizeof FFTComplex
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lsl r2, r2, #5 @ 4 * n * sizeof FFTComplex
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add r3, r2, r4
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add r4, r4, r0 @ &z[o1]
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add r2, r2, r0 @ &z[o2]
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add r3, r3, r0 @ &z[o3]
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vld1.32 {d20-d21},[r2,:128] @ {z[o2],z[o2+1]}
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movrel r12, pmmp
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vld1.32 {d22-d23},[r3,:128] @ {z[o3],z[o3+1]}
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add r5, r5, r1 @ wim
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vld1.32 {d6-d7}, [r12,:128] @ pmmp
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vswp d21, d22
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vld1.32 {d4}, [r1,:64]! @ {wre[0],wre[1]}
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sub r5, r5, #4 @ wim--
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vrev64.32 q1, q11
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vmul.f32 q11, q11, d4[1]
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vmul.f32 q1, q1, q3
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vld1.32 {d5[0]}, [r5,:32] @ d5[0] = wim[-1]
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vmla.f32 q11, q1, d5[0] @ {t1a,t2a,t5a,t6a}
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vld2.32 {d16-d17},[r0,:128] @ {z[0],z[1]}
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sub r6, r6, #1 @ n--
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vld2.32 {d18-d19},[r4,:128] @ {z[o1],z[o1+1]}
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vzip.32 q10, q11
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vadd.f32 d0, d22, d20
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vadd.f32 d1, d21, d23
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vsub.f32 d2, d21, d23
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vsub.f32 d3, d22, d20
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vsub.f32 q10, q8, q0
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vadd.f32 q8, q8, q0
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vsub.f32 q11, q9, q1
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vadd.f32 q9, q9, q1
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vst2.32 {d20-d21},[r2,:128]! @ {z[o2],z[o2+1]}
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vst2.32 {d16-d17},[r0,:128]! @ {z[0],z[1]}
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vst2.32 {d22-d23},[r3,:128]! @ {z[o3],z[o3+1]}
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vst2.32 {d18-d19},[r4,:128]! @ {z[o1],z[o1+1]}
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sub r5, r5, #8 @ wim -= 2
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1:
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vld1.32 {d20-d21},[r2,:128] @ {z[o2],z[o2+1]}
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vld1.32 {d22-d23},[r3,:128] @ {z[o3],z[o3+1]}
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vswp d21, d22
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vld1.32 {d4}, [r1]! @ {wre[0],wre[1]}
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vrev64.32 q0, q10
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vmul.f32 q10, q10, d4[0]
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vrev64.32 q1, q11
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vmul.f32 q11, q11, d4[1]
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vld1.32 {d5}, [r5] @ {wim[-1],wim[0]}
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vmul.f32 q0, q0, q3
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sub r5, r5, #8 @ wim -= 2
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vmul.f32 q1, q1, q3
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vmla.f32 q10, q0, d5[1] @ {t1,t2,t5,t6}
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vmla.f32 q11, q1, d5[0] @ {t1a,t2a,t5a,t6a}
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vld2.32 {d16-d17},[r0,:128] @ {z[0],z[1]}
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subs r6, r6, #1 @ n--
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vld2.32 {d18-d19},[r4,:128] @ {z[o1],z[o1+1]}
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vzip.32 q10, q11
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vadd.f32 d0, d22, d20
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vadd.f32 d1, d21, d23
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vsub.f32 d2, d21, d23
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vsub.f32 d3, d22, d20
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vsub.f32 q10, q8, q0
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vadd.f32 q8, q8, q0
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vsub.f32 q11, q9, q1
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vadd.f32 q9, q9, q1
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vst2.32 {d20-d21}, [r2,:128]! @ {z[o2],z[o2+1]}
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vst2.32 {d16-d17}, [r0,:128]! @ {z[0],z[1]}
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vst2.32 {d22-d23}, [r3,:128]! @ {z[o3],z[o3+1]}
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vst2.32 {d18-d19}, [r4,:128]! @ {z[o1],z[o1+1]}
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bne 1b
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pop {r4-r6,pc}
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endfunc
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.macro def_fft n, n2, n4
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.align 6
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function fft\n\()_neon
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push {r4, lr}
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mov r4, r0
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bl fft\n2\()_neon
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add r0, r4, #\n4*2*8
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bl fft\n4\()_neon
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add r0, r4, #\n4*3*8
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bl fft\n4\()_neon
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mov r0, r4
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pop {r4, lr}
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movrelx r1, X(ff_cos_\n)
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mov r2, #\n4/2
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b fft_pass_neon
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endfunc
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.endm
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def_fft 32, 16, 8
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def_fft 64, 32, 16
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def_fft 128, 64, 32
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def_fft 256, 128, 64
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def_fft 512, 256, 128
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def_fft 1024, 512, 256
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def_fft 2048, 1024, 512
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def_fft 4096, 2048, 1024
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def_fft 8192, 4096, 2048
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def_fft 16384, 8192, 4096
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def_fft 32768, 16384, 8192
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def_fft 65536, 32768, 16384
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function ff_fft_calc_neon, export=1
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ldr r2, [r0]
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sub r2, r2, #2
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movrel r3, fft_tab_neon
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ldr r3, [r3, r2, lsl #2]
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mov r0, r1
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bx r3
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endfunc
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function ff_fft_permute_neon, export=1
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push {r4,lr}
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mov r12, #1
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ldr r2, [r0] @ nbits
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ldr r3, [r0, #12] @ tmp_buf
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ldr r0, [r0, #8] @ revtab
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lsl r12, r12, r2
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mov r2, r12
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1:
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vld1.32 {d0-d1}, [r1,:128]!
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ldr r4, [r0], #4
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uxth lr, r4
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uxth r4, r4, ror #16
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add lr, r3, lr, lsl #3
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add r4, r3, r4, lsl #3
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vst1.32 {d0}, [lr,:64]
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vst1.32 {d1}, [r4,:64]
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subs r12, r12, #2
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bgt 1b
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sub r1, r1, r2, lsl #3
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1:
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vld1.32 {d0-d3}, [r3,:128]!
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vst1.32 {d0-d3}, [r1,:128]!
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subs r2, r2, #4
|
|
bgt 1b
|
|
|
|
pop {r4,pc}
|
|
endfunc
|
|
|
|
const fft_tab_neon, relocate=1
|
|
.word fft4_neon
|
|
.word fft8_neon
|
|
.word fft16_neon
|
|
.word fft32_neon
|
|
.word fft64_neon
|
|
.word fft128_neon
|
|
.word fft256_neon
|
|
.word fft512_neon
|
|
.word fft1024_neon
|
|
.word fft2048_neon
|
|
.word fft4096_neon
|
|
.word fft8192_neon
|
|
.word fft16384_neon
|
|
.word fft32768_neon
|
|
.word fft65536_neon
|
|
endconst
|
|
|
|
const pmmp, align=4
|
|
.float +1.0, -1.0, -1.0, +1.0
|
|
endconst
|
|
|
|
const mppm, align=4
|
|
.float -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2
|
|
endconst
|