mirror of
https://github.com/FFmpeg/FFmpeg.git
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38cd829dce
Currently it is done in several different ways, which might cause needless dependencies or in case of tx_float_neon.S is incorrect. Reviewed-by: Martin Storsjö <martin@martin.st> Signed-off-by: Reimar Döffinger <Reimar.Doeffinger@gmx.de>
327 lines
14 KiB
ArmAsm
327 lines
14 KiB
ArmAsm
/*
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* AArch64 NEON optimised MDCT
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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* Copyright (c) 2014 Janne Grunau <janne-libav@jannau.net>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/aarch64/asm.S"
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function ff_imdct_half_neon, export=1
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stp x19, x20, [sp, #-32]!
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AARCH64_SIGN_LINK_REGISTER
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str x30, [sp, #16]
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mov x12, #1
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ldr w14, [x0, #28] // mdct_bits
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ldr x4, [x0, #32] // tcos
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ldr x3, [x0, #8] // revtab
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lsl x12, x12, x14 // n = 1 << nbits
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lsr x14, x12, #2 // n4 = n >> 2
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add x7, x2, x12, lsl #1
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mov x12, #-16
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sub x7, x7, #16
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ld2 {v16.2s,v17.2s}, [x7], x12 // d16=x,n1 d17=x,n0
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ld2 {v0.2s,v1.2s}, [x2], #16 // d0 =m0,x d1 =m1,x
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rev64 v17.2s, v17.2s
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ld2 {v2.2s,v3.2s}, [x4], #16 // d2=c0,c1 d3=s0,s2
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fmul v6.2s, v17.2s, v2.2s
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fmul v7.2s, v0.2s, v2.2s
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1:
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subs x14, x14, #2
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ldr w6, [x3], #4
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fmul v4.2s, v0.2s, v3.2s
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fmul v5.2s, v17.2s, v3.2s
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fsub v4.2s, v6.2s, v4.2s
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fadd v5.2s, v5.2s, v7.2s
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ubfm x8, x6, #16, #31
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ubfm x6, x6, #0, #15
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add x8, x1, x8, lsl #3
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add x6, x1, x6, lsl #3
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b.eq 2f
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ld2 {v16.2s,v17.2s}, [x7], x12
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ld2 {v0.2s,v1.2s}, [x2], #16
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rev64 v17.2s, v17.2s
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ld2 {v2.2s,v3.2s}, [x4], #16 // d2=c0,c1 d3=s0,s2
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fmul v6.2s, v17.2s, v2.2s
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fmul v7.2s, v0.2s, v2.2s
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st2 {v4.s,v5.s}[0], [x6]
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st2 {v4.s,v5.s}[1], [x8]
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b 1b
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2:
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st2 {v4.s,v5.s}[0], [x6]
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st2 {v4.s,v5.s}[1], [x8]
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mov x19, x0
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mov x20, x1
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bl X(ff_fft_calc_neon)
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mov x12, #1
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ldr w14, [x19, #28] // mdct_bits
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ldr x4, [x19, #32] // tcos
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lsl x12, x12, x14 // n = 1 << nbits
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lsr x14, x12, #3 // n8 = n >> 3
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add x4, x4, x14, lsl #3
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add x6, x20, x14, lsl #3
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sub x1, x4, #16
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sub x3, x6, #16
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mov x7, #-16
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mov x8, x6
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mov x0, x3
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ld2 {v0.2s,v1.2s}, [x3], x7 // d0 =i1,r1 d1 =i0,r0
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ld2 {v20.2s,v21.2s},[x6], #16 // d20=i2,r2 d21=i3,r3
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ld2 {v16.2s,v17.2s},[x1], x7 // d16=c1,c0 d18=s1,s0
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3:
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subs x14, x14, #2
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fmul v7.2s, v0.2s, v17.2s
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ld2 {v18.2s,v19.2s},[x4], #16 // d17=c2,c3 d19=s2,s3
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fmul v4.2s, v1.2s, v17.2s
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fmul v6.2s, v21.2s, v19.2s
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fmul v5.2s, v20.2s, v19.2s
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fmul v22.2s, v1.2s, v16.2s
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fmul v23.2s, v21.2s, v18.2s
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fmul v24.2s, v0.2s, v16.2s
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fmul v25.2s, v20.2s, v18.2s
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fadd v7.2s, v7.2s, v22.2s
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fadd v5.2s, v5.2s, v23.2s
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fsub v4.2s, v4.2s, v24.2s
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fsub v6.2s, v6.2s, v25.2s
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b.eq 4f
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ld2 {v0.2s,v1.2s}, [x3], x7
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ld2 {v20.2s,v21.2s},[x6], #16
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ld2 {v16.2s,v17.2s},[x1], x7 // d16=c1,c0 d18=s1,s0
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rev64 v5.2s, v5.2s
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rev64 v7.2s, v7.2s
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st2 {v4.2s,v5.2s}, [x0], x7
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st2 {v6.2s,v7.2s}, [x8], #16
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b 3b
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4:
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rev64 v5.2s, v5.2s
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rev64 v7.2s, v7.2s
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st2 {v4.2s,v5.2s}, [x0]
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st2 {v6.2s,v7.2s}, [x8]
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ldr x30, [sp, #16]
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AARCH64_VALIDATE_LINK_REGISTER
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ldp x19, x20, [sp], #32
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ret
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endfunc
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function ff_imdct_calc_neon, export=1
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stp x19, x20, [sp, #-32]!
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AARCH64_SIGN_LINK_REGISTER
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str x30, [sp, #16]
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ldr w3, [x0, #28] // mdct_bits
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mov x19, #1
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mov x20, x1
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lsl x19, x19, x3
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add x1, x1, x19
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bl X(ff_imdct_half_neon)
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add x0, x20, x19, lsl #2
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add x1, x20, x19, lsl #1
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sub x0, x0, #8
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sub x2, x1, #16
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mov x3, #-16
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mov x6, #-8
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1:
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ld1 {v0.4s}, [x2], x3
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prfum pldl1keep, [x0, #-16]
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rev64 v0.4s, v0.4s
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ld1 {v2.2s,v3.2s}, [x1], #16
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fneg v4.4s, v0.4s
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prfum pldl1keep, [x2, #-16]
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rev64 v2.2s, v2.2s
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rev64 v3.2s, v3.2s
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ext v4.16b, v4.16b, v4.16b, #8
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st1 {v2.2s}, [x0], x6
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st1 {v3.2s}, [x0], x6
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st1 {v4.4s}, [x20], #16
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subs x19, x19, #16
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b.gt 1b
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ldr x30, [sp, #16]
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AARCH64_VALIDATE_LINK_REGISTER
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ldp x19, x20, [sp], #32
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ret
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endfunc
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function ff_mdct_calc_neon, export=1
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stp x19, x20, [sp, #-32]!
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AARCH64_SIGN_LINK_REGISTER
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str x30, [sp, #16]
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mov x12, #1
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ldr w14, [x0, #28] // mdct_bits
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ldr x4, [x0, #32] // tcos
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ldr x3, [x0, #8] // revtab
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lsl x14, x12, x14 // n = 1 << nbits
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add x7, x2, x14 // in4u
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sub x9, x7, #16 // in4d
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add x2, x7, x14, lsl #1 // in3u
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add x8, x9, x14, lsl #1 // in3d
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add x5, x4, x14, lsl #1
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sub x5, x5, #16
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sub x3, x3, #4
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mov x12, #-16
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lsr x13, x14, #1
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ld2 {v16.2s,v17.2s}, [x9], x12 // in0u0,in0u1 in4d1,in4d0
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ld2 {v18.2s,v19.2s}, [x8], x12 // in2u0,in2u1 in3d1,in3d0
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ld2 {v0.2s, v1.2s}, [x7], #16 // in4u0,in4u1 in2d1,in2d0
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rev64 v17.2s, v17.2s // in4d0,in4d1 in3d0,in3d1
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rev64 v19.2s, v19.2s // in4d0,in4d1 in3d0,in3d1
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ld2 {v2.2s, v3.2s}, [x2], #16 // in3u0,in3u1 in1d1,in1d0
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fsub v0.2s, v17.2s, v0.2s // in4d-in4u I
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ld2 {v20.2s,v21.2s}, [x4], #16 // c0,c1 s0,s1
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rev64 v1.2s, v1.2s // in2d0,in2d1 in1d0,in1d1
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rev64 v3.2s, v3.2s // in2d0,in2d1 in1d0,in1d1
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ld2 {v30.2s,v31.2s}, [x5], x12 // c2,c3 s2,s3
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fadd v2.2s, v2.2s, v19.2s // in3u+in3d -R
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fsub v16.2s, v16.2s, v1.2s // in0u-in2d R
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fadd v18.2s, v18.2s, v3.2s // in2u+in1d -I
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1:
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fmul v7.2s, v0.2s, v21.2s // I*s
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ldr w10, [x3, x13]
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fmul v6.2s, v2.2s, v20.2s // -R*c
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ldr w6, [x3, #4]!
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fmul v4.2s, v2.2s, v21.2s // -R*s
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fmul v5.2s, v0.2s, v20.2s // I*c
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fmul v24.2s, v16.2s, v30.2s // R*c
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fmul v25.2s, v18.2s, v31.2s // -I*s
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fmul v22.2s, v16.2s, v31.2s // R*s
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fmul v23.2s, v18.2s, v30.2s // I*c
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subs x14, x14, #16
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subs x13, x13, #8
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fsub v6.2s, v6.2s, v7.2s // -R*c-I*s
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fadd v7.2s, v4.2s, v5.2s // -R*s+I*c
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fsub v24.2s, v25.2s, v24.2s // I*s-R*c
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fadd v25.2s, v22.2s, v23.2s // R*s-I*c
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b.eq 1f
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mov x12, #-16
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ld2 {v16.2s,v17.2s}, [x9], x12 // in0u0,in0u1 in4d1,in4d0
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ld2 {v18.2s,v19.2s}, [x8], x12 // in2u0,in2u1 in3d1,in3d0
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fneg v7.2s, v7.2s // R*s-I*c
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ld2 {v0.2s, v1.2s}, [x7], #16 // in4u0,in4u1 in2d1,in2d0
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rev64 v17.2s, v17.2s // in4d0,in4d1 in3d0,in3d1
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rev64 v19.2s, v19.2s // in4d0,in4d1 in3d0,in3d1
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ld2 {v2.2s, v3.2s}, [x2], #16 // in3u0,in3u1 in1d1,in1d0
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fsub v0.2s, v17.2s, v0.2s // in4d-in4u I
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ld2 {v20.2s,v21.2s}, [x4], #16 // c0,c1 s0,s1
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rev64 v1.2s, v1.2s // in2d0,in2d1 in1d0,in1d1
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rev64 v3.2s, v3.2s // in2d0,in2d1 in1d0,in1d1
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ld2 {v30.2s,v31.2s}, [x5], x12 // c2,c3 s2,s3
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fadd v2.2s, v2.2s, v19.2s // in3u+in3d -R
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fsub v16.2s, v16.2s, v1.2s // in0u-in2d R
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fadd v18.2s, v18.2s, v3.2s // in2u+in1d -I
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ubfm x12, x6, #16, #31
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ubfm x6, x6, #0, #15
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add x12, x1, x12, lsl #3
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add x6, x1, x6, lsl #3
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st2 {v6.s,v7.s}[0], [x6]
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st2 {v6.s,v7.s}[1], [x12]
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ubfm x6, x10, #16, #31
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ubfm x10, x10, #0, #15
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add x6 , x1, x6, lsl #3
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add x10, x1, x10, lsl #3
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st2 {v24.s,v25.s}[0], [x10]
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st2 {v24.s,v25.s}[1], [x6]
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b 1b
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1:
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fneg v7.2s, v7.2s // R*s-I*c
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ubfm x12, x6, #16, #31
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ubfm x6, x6, #0, #15
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add x12, x1, x12, lsl #3
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add x6, x1, x6, lsl #3
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st2 {v6.s,v7.s}[0], [x6]
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st2 {v6.s,v7.s}[1], [x12]
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ubfm x6, x10, #16, #31
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ubfm x10, x10, #0, #15
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add x6 , x1, x6, lsl #3
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add x10, x1, x10, lsl #3
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st2 {v24.s,v25.s}[0], [x10]
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st2 {v24.s,v25.s}[1], [x6]
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mov x19, x0
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mov x20, x1
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bl X(ff_fft_calc_neon)
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mov x12, #1
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ldr w14, [x19, #28] // mdct_bits
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ldr x4, [x19, #32] // tcos
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lsl x12, x12, x14 // n = 1 << nbits
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lsr x14, x12, #3 // n8 = n >> 3
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add x4, x4, x14, lsl #3
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add x6, x20, x14, lsl #3
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sub x1, x4, #16
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sub x3, x6, #16
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mov x7, #-16
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mov x8, x6
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mov x0, x3
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ld2 {v0.2s,v1.2s}, [x3], x7 // d0 =r1,i1 d1 =r0,i0
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ld2 {v20.2s,v21.2s}, [x6], #16 // d20=r2,i2 d21=r3,i3
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ld2 {v16.2s,v17.2s}, [x1], x7 // c1,c0 s1,s0
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1:
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subs x14, x14, #2
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fmul v7.2s, v0.2s, v17.2s // r1*s1,r0*s0
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ld2 {v18.2s,v19.2s}, [x4], #16 // c2,c3 s2,s3
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fmul v4.2s, v1.2s, v17.2s // i1*s1,i0*s0
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fmul v6.2s, v21.2s, v19.2s // i2*s2,i3*s3
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fmul v5.2s, v20.2s, v19.2s // r2*s2,r3*s3
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fmul v24.2s, v0.2s, v16.2s // r1*c1,r0*c0
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fmul v25.2s, v20.2s, v18.2s // r2*c2,r3*c3
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fmul v22.2s, v21.2s, v18.2s // i2*c2,i3*c3
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fmul v23.2s, v1.2s, v16.2s // i1*c1,i0*c0
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fadd v4.2s, v4.2s, v24.2s // i1*s1+r1*c1,i0*s0+r0*c0
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fadd v6.2s, v6.2s, v25.2s // i2*s2+r2*c2,i3*s3+r3*c3
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fsub v5.2s, v22.2s, v5.2s // i2*c2-r2*s2,i3*c3-r3*s3
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fsub v7.2s, v23.2s, v7.2s // i1*c1-r1*s1,i0*c0-r0*s0
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fneg v4.2s, v4.2s
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fneg v6.2s, v6.2s
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b.eq 1f
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ld2 {v0.2s, v1.2s}, [x3], x7
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ld2 {v20.2s,v21.2s}, [x6], #16
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ld2 {v16.2s,v17.2s}, [x1], x7 // c1,c0 s1,s0
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rev64 v5.2s, v5.2s
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rev64 v7.2s, v7.2s
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st2 {v4.2s,v5.2s}, [x0], x7
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st2 {v6.2s,v7.2s}, [x8], #16
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b 1b
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1:
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rev64 v5.2s, v5.2s
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rev64 v7.2s, v7.2s
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st2 {v4.2s,v5.2s}, [x0]
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st2 {v6.2s,v7.2s}, [x8]
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ldr x30, [sp, #16]
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AARCH64_VALIDATE_LINK_REGISTER
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ldp x19, x20, [sp], #32
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ret
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endfunc
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