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70db14376c
Before: Cortex A53 A72 A73 Graviton 2 Graviton 3 hscale_8_to_15_width8_neon: 8273.0 4602.5 4289.5 2429.7 1629.1 hscale_8_to_15_width16_neon: 12405.7 6803.0 6359.0 3549.0 2378.4 hscale_8_to_15_width32_neon: 21258.7 11491.7 11469.2 5797.2 3919.6 hscale_8_to_15_width40_neon: 25652.0 14173.7 12488.2 6893.5 4810.4 After: hscale_8_to_15_width8_neon: 7633.0 3981.5 3350.2 1980.7 1261.1 hscale_8_to_15_width16_neon: 11666.7 5951.0 5512.0 3080.7 2131.4 hscale_8_to_15_width32_neon: 20900.7 10733.2 9481.7 5275.2 3862.1 hscale_8_to_15_width40_neon: 24826.0 13536.2 11502.0 6397.2 4731.9 Thus, this gives overall a 8-29% speedup for the smaller filter sizes, around 1-8% for the larger filter sizes. Inspired by a patch by Jonathan Swinney <jswinney@amazon.com>. Signed-off-by: Martin Storsjö <martin@martin.st>
73 lines
5.1 KiB
ArmAsm
73 lines
5.1 KiB
ArmAsm
/*
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* Copyright (c) 2016 Clément Bœsch <clement stupeflix.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/aarch64/asm.S"
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function ff_hscale_8_to_15_neon, export=1
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sbfiz x7, x6, #1, #32 // filterSize*2 (*2 because int16)
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1: ldr w8, [x5], #4 // filterPos[idx]
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ldr w0, [x5], #4 // filterPos[idx + 1]
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ldr w11, [x5], #4 // filterPos[idx + 2]
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ldr w9, [x5], #4 // filterPos[idx + 3]
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mov x16, x4 // filter0 = filter
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add x12, x16, x7 // filter1 = filter0 + filterSize*2
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add x13, x12, x7 // filter2 = filter1 + filterSize*2
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add x4, x13, x7 // filter3 = filter2 + filterSize*2
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movi v0.2D, #0 // val sum part 1 (for dst[0])
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movi v1.2D, #0 // val sum part 2 (for dst[1])
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movi v2.2D, #0 // val sum part 3 (for dst[2])
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movi v3.2D, #0 // val sum part 4 (for dst[3])
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add x17, x3, w8, UXTW // srcp + filterPos[0]
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add x8, x3, w0, UXTW // srcp + filterPos[1]
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add x0, x3, w11, UXTW // srcp + filterPos[2]
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add x11, x3, w9, UXTW // srcp + filterPos[3]
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mov w15, w6 // filterSize counter
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2: ld1 {v4.8B}, [x17], #8 // srcp[filterPos[0] + {0..7}]
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ld1 {v5.8H}, [x16], #16 // load 8x16-bit filter values, part 1
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ld1 {v6.8B}, [x8], #8 // srcp[filterPos[1] + {0..7}]
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ld1 {v7.8H}, [x12], #16 // load 8x16-bit at filter+filterSize
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uxtl v4.8H, v4.8B // unpack part 1 to 16-bit
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smlal v0.4S, v4.4H, v5.4H // v0 accumulates srcp[filterPos[0] + {0..3}] * filter[{0..3}]
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smlal2 v0.4S, v4.8H, v5.8H // v0 accumulates srcp[filterPos[0] + {4..7}] * filter[{4..7}]
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ld1 {v16.8B}, [x0], #8 // srcp[filterPos[2] + {0..7}]
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ld1 {v17.8H}, [x13], #16 // load 8x16-bit at filter+2*filterSize
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uxtl v6.8H, v6.8B // unpack part 2 to 16-bit
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smlal v1.4S, v6.4H, v7.4H // v1 accumulates srcp[filterPos[1] + {0..3}] * filter[{0..3}]
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uxtl v16.8H, v16.8B // unpack part 3 to 16-bit
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smlal v2.4S, v16.4H, v17.4H // v2 accumulates srcp[filterPos[2] + {0..3}] * filter[{0..3}]
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smlal2 v2.4S, v16.8H, v17.8H // v2 accumulates srcp[filterPos[2] + {4..7}] * filter[{4..7}]
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ld1 {v18.8B}, [x11], #8 // srcp[filterPos[3] + {0..7}]
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smlal2 v1.4S, v6.8H, v7.8H // v1 accumulates srcp[filterPos[1] + {4..7}] * filter[{4..7}]
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ld1 {v19.8H}, [x4], #16 // load 8x16-bit at filter+3*filterSize
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subs w15, w15, #8 // j -= 8: processed 8/filterSize
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uxtl v18.8H, v18.8B // unpack part 4 to 16-bit
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smlal v3.4S, v18.4H, v19.4H // v3 accumulates srcp[filterPos[3] + {0..3}] * filter[{0..3}]
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smlal2 v3.4S, v18.8H, v19.8H // v3 accumulates srcp[filterPos[3] + {4..7}] * filter[{4..7}]
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b.gt 2b // inner loop if filterSize not consumed completely
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addp v0.4S, v0.4S, v1.4S // part01 horizontal pair adding
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addp v2.4S, v2.4S, v3.4S // part23 horizontal pair adding
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addp v0.4S, v0.4S, v2.4S // part0123 horizontal pair adding
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subs w2, w2, #4 // dstW -= 4
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sqshrn v0.4H, v0.4S, #7 // shift and clip the 2x16-bit final values
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st1 {v0.4H}, [x1], #8 // write to destination part0123
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b.gt 1b // loop until end of line
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ret
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endfunc
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