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a7acab6cda
* qatar/master: vc1dec: Remove separate scaling function for interlaced field MVs vc1dec: Invoke edge_emulation regardless of MV precision x86: Use consistent 3dnowext function and macro name suffixes g723_1: scale output as supposed for the case with postfilter disabled g723_1: increase excitation storage by 4 g723_1: fix upper bound parameter from inverse maximum autocorrelation g723_1: make scale_vector() behave like the reference g723_1: fix off-by-one error in normalize_bits() g723_1: save/restore excitation with offset to store LPC history wmapro: prevent division by zero when sample rate is unspecified x86: proresdsp: improve SIGNEXTEND macro comments x86: h264dsp: K&R formatting cosmetics LICENSE: Document all GPL files Conflicts: libavcodec/g723_1.c libavcodec/wmaprodec.c libavcodec/x86/h264dsp_mmx.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
328 lines
9.8 KiB
NASM
328 lines
9.8 KiB
NASM
;******************************************************************************
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;* x86-SIMD-optimized IDCT for prores
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;* this is identical to "simple" IDCT written by Michael Niedermayer
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;* except for the clip range
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;*
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;* Copyright (c) 2011 Ronald S. Bultje <rsbultje@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* 51, Inc., Foundation Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "x86inc.asm"
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%include "x86util.asm"
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%define W1sh2 22725 ; W1 = 90901 = 22725<<2 + 1
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%define W2sh2 21407 ; W2 = 85627 = 21407<<2 - 1
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%define W3sh2 19265 ; W3 = 77062 = 19265<<2 + 2
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%define W4sh2 16384 ; W4 = 65535 = 16384<<2 - 1
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%define W5sh2 12873 ; W5 = 51491 = 12873<<2 - 1
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%define W6sh2 8867 ; W6 = 35468 = 8867<<2
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%define W7sh2 4520 ; W7 = 18081 = 4520<<2 + 1
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%if ARCH_X86_64
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SECTION_RODATA
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w4_plus_w2: times 4 dw W4sh2, +W2sh2
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w4_min_w2: times 4 dw W4sh2, -W2sh2
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w4_plus_w6: times 4 dw W4sh2, +W6sh2
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w4_min_w6: times 4 dw W4sh2, -W6sh2
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w1_plus_w3: times 4 dw W1sh2, +W3sh2
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w3_min_w1: times 4 dw W3sh2, -W1sh2
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w7_plus_w3: times 4 dw W7sh2, +W3sh2
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w3_min_w7: times 4 dw W3sh2, -W7sh2
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w1_plus_w5: times 4 dw W1sh2, +W5sh2
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w5_min_w1: times 4 dw W5sh2, -W1sh2
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w5_plus_w7: times 4 dw W5sh2, +W7sh2
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w7_min_w5: times 4 dw W7sh2, -W5sh2
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pw_88: times 8 dw 0x2008
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cextern pw_1
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cextern pw_4
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cextern pw_512
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cextern pw_1019
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section .text align=16
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; interleave data while maintaining source
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; %1=type, %2=dstlo, %3=dsthi, %4=src, %5=interleave
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%macro SBUTTERFLY3 5
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punpckl%1 m%2, m%4, m%5
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punpckh%1 m%3, m%4, m%5
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%endmacro
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; %1/%2=src1/dst1, %3/%4=dst2, %5/%6=src2, %7=shift
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; action: %3/%4 = %1/%2 - %5/%6; %1/%2 += %5/%6
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; %1/%2/%3/%4 >>= %7; dword -> word (in %1/%3)
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%macro SUMSUB_SHPK 7
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psubd %3, %1, %5 ; { a0 - b0 }[0-3]
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psubd %4, %2, %6 ; { a0 - b0 }[4-7]
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paddd %1, %5 ; { a0 + b0 }[0-3]
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paddd %2, %6 ; { a0 + b0 }[4-7]
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psrad %1, %7
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psrad %2, %7
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psrad %3, %7
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psrad %4, %7
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packssdw %1, %2 ; row[0]
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packssdw %3, %4 ; row[7]
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%endmacro
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; %1 = row or col (for rounding variable)
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; %2 = number of bits to shift at the end
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%macro IDCT_1D 2
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; a0 = (W4 * row[0]) + (1 << (15 - 1));
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; a1 = a0;
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; a2 = a0;
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; a3 = a0;
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; a0 += W2 * row[2];
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; a1 += W6 * row[2];
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; a2 -= W6 * row[2];
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; a3 -= W2 * row[2];
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%ifidn %1, col
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paddw m10,[pw_88]
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%endif
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%ifidn %1, row
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paddw m10,[pw_1]
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%endif
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SBUTTERFLY3 wd, 0, 1, 10, 8 ; { row[0], row[2] }[0-3]/[4-7]
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pmaddwd m2, m0, [w4_plus_w6]
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pmaddwd m3, m1, [w4_plus_w6]
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pmaddwd m4, m0, [w4_min_w6]
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pmaddwd m5, m1, [w4_min_w6]
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pmaddwd m6, m0, [w4_min_w2]
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pmaddwd m7, m1, [w4_min_w2]
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pmaddwd m0, [w4_plus_w2]
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pmaddwd m1, [w4_plus_w2]
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; a0: -1*row[0]-1*row[2]
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; a1: -1*row[0]
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; a2: -1*row[0]
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; a3: -1*row[0]+1*row[2]
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; a0 += W4*row[4] + W6*row[6]; i.e. -1*row[4]
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; a1 -= W4*row[4] + W2*row[6]; i.e. -1*row[4]-1*row[6]
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; a2 -= W4*row[4] - W2*row[6]; i.e. -1*row[4]+1*row[6]
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; a3 += W4*row[4] - W6*row[6]; i.e. -1*row[4]
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SBUTTERFLY3 wd, 8, 9, 13, 12 ; { row[4], row[6] }[0-3]/[4-7]
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pmaddwd m10, m8, [w4_plus_w6]
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pmaddwd m11, m9, [w4_plus_w6]
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paddd m0, m10 ; a0[0-3]
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paddd m1, m11 ; a0[4-7]
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pmaddwd m10, m8, [w4_min_w6]
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pmaddwd m11, m9, [w4_min_w6]
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paddd m6, m10 ; a3[0-3]
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paddd m7, m11 ; a3[4-7]
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pmaddwd m10, m8, [w4_min_w2]
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pmaddwd m11, m9, [w4_min_w2]
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pmaddwd m8, [w4_plus_w2]
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pmaddwd m9, [w4_plus_w2]
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psubd m4, m10 ; a2[0-3] intermediate
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psubd m5, m11 ; a2[4-7] intermediate
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psubd m2, m8 ; a1[0-3] intermediate
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psubd m3, m9 ; a1[4-7] intermediate
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; load/store
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mova [r2+ 0], m0
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mova [r2+ 32], m2
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mova [r2+ 64], m4
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mova [r2+ 96], m6
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mova m10,[r2+ 16] ; { row[1] }[0-7]
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mova m8, [r2+ 48] ; { row[3] }[0-7]
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mova m13,[r2+ 80] ; { row[5] }[0-7]
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mova m14,[r2+112] ; { row[7] }[0-7]
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mova [r2+ 16], m1
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mova [r2+ 48], m3
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mova [r2+ 80], m5
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mova [r2+112], m7
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%ifidn %1, row
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pmullw m10,[r3+ 16]
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pmullw m8, [r3+ 48]
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pmullw m13,[r3+ 80]
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pmullw m14,[r3+112]
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%endif
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; b0 = MUL(W1, row[1]);
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; MAC(b0, W3, row[3]);
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; b1 = MUL(W3, row[1]);
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; MAC(b1, -W7, row[3]);
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; b2 = MUL(W5, row[1]);
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; MAC(b2, -W1, row[3]);
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; b3 = MUL(W7, row[1]);
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; MAC(b3, -W5, row[3]);
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SBUTTERFLY3 wd, 0, 1, 10, 8 ; { row[1], row[3] }[0-3]/[4-7]
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pmaddwd m2, m0, [w3_min_w7]
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pmaddwd m3, m1, [w3_min_w7]
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pmaddwd m4, m0, [w5_min_w1]
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pmaddwd m5, m1, [w5_min_w1]
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pmaddwd m6, m0, [w7_min_w5]
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pmaddwd m7, m1, [w7_min_w5]
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pmaddwd m0, [w1_plus_w3]
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pmaddwd m1, [w1_plus_w3]
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; b0: +1*row[1]+2*row[3]
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; b1: +2*row[1]-1*row[3]
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; b2: -1*row[1]-1*row[3]
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; b3: +1*row[1]+1*row[3]
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; MAC(b0, W5, row[5]);
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; MAC(b0, W7, row[7]);
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; MAC(b1, -W1, row[5]);
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; MAC(b1, -W5, row[7]);
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; MAC(b2, W7, row[5]);
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; MAC(b2, W3, row[7]);
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; MAC(b3, W3, row[5]);
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; MAC(b3, -W1, row[7]);
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SBUTTERFLY3 wd, 8, 9, 13, 14 ; { row[5], row[7] }[0-3]/[4-7]
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; b0: -1*row[5]+1*row[7]
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; b1: -1*row[5]+1*row[7]
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; b2: +1*row[5]+2*row[7]
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; b3: +2*row[5]-1*row[7]
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pmaddwd m10, m8, [w1_plus_w5]
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pmaddwd m11, m9, [w1_plus_w5]
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pmaddwd m12, m8, [w5_plus_w7]
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pmaddwd m13, m9, [w5_plus_w7]
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psubd m2, m10 ; b1[0-3]
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psubd m3, m11 ; b1[4-7]
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paddd m0, m12 ; b0[0-3]
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paddd m1, m13 ; b0[4-7]
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pmaddwd m12, m8, [w7_plus_w3]
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pmaddwd m13, m9, [w7_plus_w3]
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pmaddwd m8, [w3_min_w1]
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pmaddwd m9, [w3_min_w1]
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paddd m4, m12 ; b2[0-3]
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paddd m5, m13 ; b2[4-7]
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paddd m6, m8 ; b3[0-3]
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paddd m7, m9 ; b3[4-7]
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; row[0] = (a0 + b0) >> 15;
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; row[7] = (a0 - b0) >> 15;
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; row[1] = (a1 + b1) >> 15;
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; row[6] = (a1 - b1) >> 15;
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; row[2] = (a2 + b2) >> 15;
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; row[5] = (a2 - b2) >> 15;
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; row[3] = (a3 + b3) >> 15;
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; row[4] = (a3 - b3) >> 15;
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mova m8, [r2+ 0] ; a0[0-3]
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mova m9, [r2+16] ; a0[4-7]
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SUMSUB_SHPK m8, m9, m10, m11, m0, m1, %2
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mova m0, [r2+32] ; a1[0-3]
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mova m1, [r2+48] ; a1[4-7]
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SUMSUB_SHPK m0, m1, m9, m11, m2, m3, %2
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mova m1, [r2+64] ; a2[0-3]
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mova m2, [r2+80] ; a2[4-7]
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SUMSUB_SHPK m1, m2, m11, m3, m4, m5, %2
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mova m2, [r2+96] ; a3[0-3]
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mova m3, [r2+112] ; a3[4-7]
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SUMSUB_SHPK m2, m3, m4, m5, m6, m7, %2
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%endmacro
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; void prores_idct_put_10_<opt>(uint8_t *pixels, int stride,
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; DCTELEM *block, const int16_t *qmat);
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%macro idct_put_fn 1
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cglobal prores_idct_put_10, 4, 4, %1
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movsxd r1, r1d
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pxor m15, m15 ; zero
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; for (i = 0; i < 8; i++)
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; idctRowCondDC(block + i*8);
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mova m10,[r2+ 0] ; { row[0] }[0-7]
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mova m8, [r2+32] ; { row[2] }[0-7]
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mova m13,[r2+64] ; { row[4] }[0-7]
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mova m12,[r2+96] ; { row[6] }[0-7]
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pmullw m10,[r3+ 0]
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pmullw m8, [r3+32]
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pmullw m13,[r3+64]
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pmullw m12,[r3+96]
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IDCT_1D row, 15
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; transpose for second part of IDCT
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TRANSPOSE8x8W 8, 0, 1, 2, 4, 11, 9, 10, 3
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mova [r2+ 16], m0
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mova [r2+ 48], m2
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mova [r2+ 80], m11
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mova [r2+112], m10
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SWAP 8, 10
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SWAP 1, 8
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SWAP 4, 13
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SWAP 9, 12
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; for (i = 0; i < 8; i++)
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; idctSparseColAdd(dest + i, line_size, block + i);
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IDCT_1D col, 18
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; clip/store
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mova m3, [pw_4]
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mova m5, [pw_1019]
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pmaxsw m8, m3
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pmaxsw m0, m3
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pmaxsw m1, m3
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pmaxsw m2, m3
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pmaxsw m4, m3
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pmaxsw m11, m3
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pmaxsw m9, m3
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pmaxsw m10, m3
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pminsw m8, m5
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pminsw m0, m5
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pminsw m1, m5
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pminsw m2, m5
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pminsw m4, m5
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pminsw m11, m5
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pminsw m9, m5
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pminsw m10, m5
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lea r2, [r1*3]
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mova [r0 ], m8
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mova [r0+r1 ], m0
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mova [r0+r1*2], m1
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mova [r0+r2 ], m2
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lea r0, [r0+r1*4]
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mova [r0 ], m4
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mova [r0+r1 ], m11
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mova [r0+r1*2], m9
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mova [r0+r2 ], m10
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RET
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%endmacro
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%macro SIGNEXTEND 2-3
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%if cpuflag(sse4) ; dstlow, dsthigh
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movhlps %2, %1
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pmovsxwd %1, %1
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pmovsxwd %2, %2
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%elif cpuflag(sse2) ; dstlow, dsthigh, tmp
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pxor %3, %3
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pcmpgtw %3, %1
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mova %2, %1
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punpcklwd %1, %3
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punpckhwd %2, %3
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%endif
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%endmacro
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INIT_XMM sse2
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idct_put_fn 16
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INIT_XMM sse4
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idct_put_fn 16
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%if HAVE_AVX
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INIT_XMM avx
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idct_put_fn 16
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%endif
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%endif
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