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5e826fd65e
All our ARM asm preserves alignment so setting this attribute in a common location is simpler. This removes numerous warnings when linking with armcc. Signed-off-by: Mans Rullgard <mans@mansr.com>
111 lines
4.0 KiB
ArmAsm
111 lines
4.0 KiB
ArmAsm
/*
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* ARM NEON optimised Float DSP functions
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "asm.S"
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function ff_vector_fmul_neon, export=1
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subs r3, r3, #8
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vld1.32 {d0-d3}, [r1,:128]!
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vld1.32 {d4-d7}, [r2,:128]!
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vmul.f32 q8, q0, q2
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vmul.f32 q9, q1, q3
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beq 3f
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bics ip, r3, #15
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beq 2f
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1: subs ip, ip, #16
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vld1.32 {d0-d1}, [r1,:128]!
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vld1.32 {d4-d5}, [r2,:128]!
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vmul.f32 q10, q0, q2
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vld1.32 {d2-d3}, [r1,:128]!
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vld1.32 {d6-d7}, [r2,:128]!
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vmul.f32 q11, q1, q3
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vst1.32 {d16-d19},[r0,:128]!
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vld1.32 {d0-d1}, [r1,:128]!
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vld1.32 {d4-d5}, [r2,:128]!
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vmul.f32 q8, q0, q2
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vld1.32 {d2-d3}, [r1,:128]!
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vld1.32 {d6-d7}, [r2,:128]!
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vmul.f32 q9, q1, q3
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vst1.32 {d20-d23},[r0,:128]!
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bne 1b
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ands r3, r3, #15
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beq 3f
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2: vld1.32 {d0-d1}, [r1,:128]!
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vld1.32 {d4-d5}, [r2,:128]!
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vst1.32 {d16-d17},[r0,:128]!
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vmul.f32 q8, q0, q2
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vld1.32 {d2-d3}, [r1,:128]!
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vld1.32 {d6-d7}, [r2,:128]!
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vst1.32 {d18-d19},[r0,:128]!
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vmul.f32 q9, q1, q3
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3: vst1.32 {d16-d19},[r0,:128]!
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bx lr
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endfunc
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function ff_vector_fmac_scalar_neon, export=1
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VFP len .req r2
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VFP acc .req r3
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NOVFP len .req r3
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NOVFP acc .req r2
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VFP vdup.32 q15, d0[0]
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NOVFP vdup.32 q15, r2
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bics r12, len, #15
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mov acc, r0
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beq 3f
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vld1.32 {q0}, [r1,:128]!
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vld1.32 {q8}, [acc,:128]!
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vld1.32 {q1}, [r1,:128]!
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vld1.32 {q9}, [acc,:128]!
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1: vmla.f32 q8, q0, q15
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vld1.32 {q2}, [r1,:128]!
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vld1.32 {q10}, [acc,:128]!
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vmla.f32 q9, q1, q15
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vld1.32 {q3}, [r1,:128]!
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vld1.32 {q11}, [acc,:128]!
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vmla.f32 q10, q2, q15
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vst1.32 {q8}, [r0,:128]!
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vmla.f32 q11, q3, q15
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vst1.32 {q9}, [r0,:128]!
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subs r12, r12, #16
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beq 2f
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vld1.32 {q0}, [r1,:128]!
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vld1.32 {q8}, [acc,:128]!
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vst1.32 {q10}, [r0,:128]!
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vld1.32 {q1}, [r1,:128]!
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vld1.32 {q9}, [acc,:128]!
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vst1.32 {q11}, [r0,:128]!
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b 1b
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2: vst1.32 {q10}, [r0,:128]!
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vst1.32 {q11}, [r0,:128]!
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ands len, len, #15
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it eq
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bxeq lr
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3: vld1.32 {q0}, [r1,:128]!
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vld1.32 {q8}, [acc,:128]!
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vmla.f32 q8, q0, q15
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vst1.32 {q8}, [r0,:128]!
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subs len, len, #4
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bgt 3b
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bx lr
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.unreq len
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endfunc
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