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https://github.com/FFmpeg/FFmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
293 lines
8.6 KiB
NASM
293 lines
8.6 KiB
NASM
;******************************************************************************
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;* VC1 motion compensation optimizations
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;* Copyright (c) 2007 Christophe GISQUET <christophe.gisquet@free.fr>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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cextern pw_9
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cextern pw_128
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SECTION .text
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%if HAVE_MMX_INLINE
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; XXX some of these macros are not used right now, but they will in the future
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; when more functions are ported.
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%macro OP_PUT 2 ; dst, src
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%endmacro
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%macro OP_AVG 2 ; dst, src
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pavgb %1, %2
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%endmacro
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%macro NORMALIZE_MMX 1 ; shift
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paddw m3, m7 ; +bias-r
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paddw m4, m7 ; +bias-r
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psraw m3, %1
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psraw m4, %1
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%endmacro
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%macro TRANSFER_DO_PACK 2 ; op, dst
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packuswb m3, m4
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%1 m3, [%2]
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mova [%2], m3
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%endmacro
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%macro TRANSFER_DONT_PACK 2 ; op, dst
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%1 m3, [%2]
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%1 m3, [%2 + mmsize]
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mova [%2], m3
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mova [mmsize + %2], m4
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%endmacro
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; see MSPEL_FILTER13_CORE for use as UNPACK macro
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%macro DO_UNPACK 1 ; reg
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punpcklbw %1, m0
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%endmacro
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%macro DONT_UNPACK 1 ; reg
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%endmacro
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; Compute the rounder 32-r or 8-r and unpacks it to m7
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%macro LOAD_ROUNDER_MMX 1 ; round
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movd m7, %1
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punpcklwd m7, m7
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punpckldq m7, m7
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%endmacro
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%macro SHIFT2_LINE 5 ; off, r0, r1, r2, r3
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paddw m%3, m%4
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movh m%2, [srcq + stride_neg2]
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pmullw m%3, m6
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punpcklbw m%2, m0
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movh m%5, [srcq + strideq]
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psubw m%3, m%2
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punpcklbw m%5, m0
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paddw m%3, m7
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psubw m%3, m%5
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psraw m%3, shift
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movu [dstq + %1], m%3
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add srcq, strideq
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%endmacro
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INIT_MMX mmx
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; void ff_vc1_put_ver_16b_shift2_mmx(int16_t *dst, const uint8_t *src,
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; x86_reg stride, int rnd, int64_t shift)
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; Sacrificing m6 makes it possible to pipeline loads from src
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%if ARCH_X86_32
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cglobal vc1_put_ver_16b_shift2, 3,6,0, dst, src, stride
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DECLARE_REG_TMP 3, 4, 5
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%define rnd r3mp
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%define shift qword r4m
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%else ; X86_64
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cglobal vc1_put_ver_16b_shift2, 4,7,0, dst, src, stride
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DECLARE_REG_TMP 4, 5, 6
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%define rnd r3d
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; We need shift either in memory or in a mm reg as it's used in psraw
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; On WIN64, the arg is already on the stack
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; On UNIX64, m5 doesn't seem to be used
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%if WIN64
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%define shift r4mp
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%else ; UNIX64
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%define shift m5
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mova shift, r4q
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%endif ; WIN64
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%endif ; X86_32
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%define stride_neg2 t0q
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%define stride_9minus4 t1q
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%define i t2q
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mov stride_neg2, strideq
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neg stride_neg2
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add stride_neg2, stride_neg2
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lea stride_9minus4, [strideq * 9 - 4]
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mov i, 3
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LOAD_ROUNDER_MMX rnd
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mova m6, [pw_9]
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pxor m0, m0
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.loop:
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movh m2, [srcq]
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add srcq, strideq
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movh m3, [srcq]
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punpcklbw m2, m0
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punpcklbw m3, m0
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SHIFT2_LINE 0, 1, 2, 3, 4
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SHIFT2_LINE 24, 2, 3, 4, 1
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SHIFT2_LINE 48, 3, 4, 1, 2
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SHIFT2_LINE 72, 4, 1, 2, 3
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SHIFT2_LINE 96, 1, 2, 3, 4
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SHIFT2_LINE 120, 2, 3, 4, 1
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SHIFT2_LINE 144, 3, 4, 1, 2
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SHIFT2_LINE 168, 4, 1, 2, 3
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sub srcq, stride_9minus4
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add dstq, 8
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dec i
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jnz .loop
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RET
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%undef rnd
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%undef shift
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%undef stride_neg2
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%undef stride_9minus4
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%undef i
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; void ff_vc1_*_hor_16b_shift2_mmx(uint8_t *dst, x86_reg stride,
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; const int16_t *src, int rnd);
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; Data is already unpacked, so some operations can directly be made from
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; memory.
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%macro HOR_16B_SHIFT2 2 ; op, opname
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cglobal vc1_%2_hor_16b_shift2, 4, 5, 0, dst, stride, src, rnd, h
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mov hq, 8
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sub srcq, 2
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sub rndd, (-1+9+9-1) * 1024 ; add -1024 bias
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LOAD_ROUNDER_MMX rndd
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mova m5, [pw_9]
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mova m6, [pw_128]
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pxor m0, m0
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.loop:
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mova m1, [srcq + 2 * 0]
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mova m2, [srcq + 2 * 0 + mmsize]
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mova m3, [srcq + 2 * 1]
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mova m4, [srcq + 2 * 1 + mmsize]
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paddw m3, [srcq + 2 * 2]
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paddw m4, [srcq + 2 * 2 + mmsize]
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paddw m1, [srcq + 2 * 3]
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paddw m2, [srcq + 2 * 3 + mmsize]
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pmullw m3, m5
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pmullw m4, m5
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psubw m3, m1
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psubw m4, m2
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NORMALIZE_MMX 7
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; remove bias
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paddw m3, m6
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paddw m4, m6
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TRANSFER_DO_PACK %1, dstq
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add srcq, 24
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add dstq, strideq
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dec hq
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jnz .loop
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RET
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%endmacro
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INIT_MMX mmx
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HOR_16B_SHIFT2 OP_PUT, put
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INIT_MMX mmxext
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HOR_16B_SHIFT2 OP_AVG, avg
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%endif ; HAVE_MMX_INLINE
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%macro INV_TRANS_INIT 0
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movsxdifnidn linesizeq, linesized
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movd m0, blockd
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SPLATW m0, m0
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pxor m1, m1
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psubw m1, m0
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packuswb m0, m0
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packuswb m1, m1
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DEFINE_ARGS dest, linesize, linesize3
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lea linesize3q, [linesizeq*3]
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%endmacro
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%macro INV_TRANS_PROCESS 1
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mov%1 m2, [destq+linesizeq*0]
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mov%1 m3, [destq+linesizeq*1]
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mov%1 m4, [destq+linesizeq*2]
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mov%1 m5, [destq+linesize3q]
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paddusb m2, m0
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paddusb m3, m0
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paddusb m4, m0
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paddusb m5, m0
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psubusb m2, m1
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psubusb m3, m1
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psubusb m4, m1
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psubusb m5, m1
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mov%1 [linesizeq*0+destq], m2
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mov%1 [linesizeq*1+destq], m3
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mov%1 [linesizeq*2+destq], m4
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mov%1 [linesize3q +destq], m5
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%endmacro
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; ff_vc1_inv_trans_?x?_dc_mmxext(uint8_t *dest, ptrdiff_t linesize, int16_t *block)
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INIT_MMX mmxext
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cglobal vc1_inv_trans_4x4_dc, 3,4,0, dest, linesize, block
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movsx r3d, WORD [blockq]
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mov blockd, r3d ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+4] ; 17 * dc + 4
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sar blockd, 3 ; >> 3
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mov r3d, blockd ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+64] ; 17 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS h
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_4x8_dc, 3,4,0, dest, linesize, block
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movsx r3d, WORD [blockq]
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mov blockd, r3d ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+4] ; 17 * dc + 4
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sar blockd, 3 ; >> 3
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shl blockd, 2 ; 4 * dc
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lea blockd, [blockq*3+64] ; 12 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS h
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lea destq, [destq+linesizeq*4]
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INV_TRANS_PROCESS h
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_8x4_dc, 3,4,0, dest, linesize, block
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movsx blockd, WORD [blockq] ; dc
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lea blockd, [blockq*3+1] ; 3 * dc + 1
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sar blockd, 1 ; >> 1
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mov r3d, blockd ; dc
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shl blockd, 4 ; 16 * dc
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lea blockd, [blockq+r3+64] ; 17 * dc + 64
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sar blockd, 7 ; >> 7
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INV_TRANS_INIT
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INV_TRANS_PROCESS a
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RET
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INIT_MMX mmxext
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cglobal vc1_inv_trans_8x8_dc, 3,3,0, dest, linesize, block
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movsx blockd, WORD [blockq] ; dc
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lea blockd, [blockq*3+1] ; 3 * dc + 1
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sar blockd, 1 ; >> 1
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lea blockd, [blockq*3+16] ; 3 * dc + 16
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sar blockd, 5 ; >> 5
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INV_TRANS_INIT
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INV_TRANS_PROCESS a
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lea destq, [destq+linesizeq*4]
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INV_TRANS_PROCESS a
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RET
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