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37961044c6
These bits are set by exceptions in NEON instructions. Also print the differing bits when FPSCR is clobbered, and use bic instead of lsl, for clearing the topmost bits. Signed-off-by: Martin Storsjö <martin@martin.st>
169 lines
4.3 KiB
ArmAsm
169 lines
4.3 KiB
ArmAsm
/****************************************************************************
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* Assembly testing and benchmarking tool
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* Copyright (c) 2015 Martin Storsjo
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* Copyright (c) 2015 Janne Grunau
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
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*****************************************************************************/
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#include "libavutil/arm/asm.S"
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/* override fpu so that NEON instructions are rejected */
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#if HAVE_VFP
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.fpu vfp
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ELF .eabi_attribute 10, 0 @ suppress Tag_FP_arch
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#endif
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const register_init, align=3
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.quad 0x21f86d66c8ca00ce
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.quad 0x75b6ba21077c48ad
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.quad 0xed56bb2dcb3c7736
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.quad 0x8bda43d3fd1a7e06
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.quad 0xb64a9c9e5d318408
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.quad 0xdf9a54b303f1d3a3
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.quad 0x4a75479abd64e097
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.quad 0x249214109d5d1c88
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endconst
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const error_message_fpscr
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.asciz "failed to preserve register FPSCR, changed bits: %x"
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error_message_gpr:
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.asciz "failed to preserve register r%d"
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error_message_vfp:
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.asciz "failed to preserve register d%d"
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endconst
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@ max number of args used by any asm function.
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#define MAX_ARGS 15
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#define ARG_STACK 4*(MAX_ARGS - 2)
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@ align the used stack space to 8 to preserve the stack alignment
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#define ARG_STACK_A (((ARG_STACK + pushed + 7) & ~7) - pushed)
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.macro clobbercheck variant
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.equ pushed, 4*9
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function checkasm_checked_call_\variant, export=1
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push {r4-r11, lr}
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.ifc \variant, vfp
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vpush {d8-d15}
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fmrx r4, FPSCR
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push {r4}
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.equ pushed, pushed + 16*4 + 4
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.endif
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movrel r12, register_init
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.ifc \variant, vfp
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vldm r12, {d8-d15}
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.endif
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ldm r12, {r4-r11}
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sub sp, sp, #ARG_STACK_A
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.equ pos, 0
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.rept MAX_ARGS-2
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ldr r12, [sp, #ARG_STACK_A + pushed + 8 + pos]
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str r12, [sp, #pos]
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.equ pos, pos + 4
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.endr
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mov r12, r0
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mov r0, r2
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mov r1, r3
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ldrd r2, r3, [sp, #ARG_STACK_A + pushed]
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blx r12
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add sp, sp, #ARG_STACK_A
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push {r0, r1}
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movrel r12, register_init
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.ifc \variant, vfp
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.macro check_reg_vfp, dreg, offset
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ldrd r2, r3, [r12, #8 * (\offset)]
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vmov r0, lr, \dreg
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eor r2, r2, r0
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eor r3, r3, lr
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orrs r2, r2, r3
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bne 4f
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.endm
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.irp n, 8, 9, 10, 11, 12, 13, 14, 15
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@ keep track of the checked double/SIMD register
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mov r1, #\n
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check_reg_vfp d\n, \n-8
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.endr
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.purgem check_reg_vfp
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fmrx r1, FPSCR
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ldr r3, [sp, #8]
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eor r1, r1, r3
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@ Ignore changes in bits 0-4 and 7
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bic r1, r1, #0x9f
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@ Ignore changes in the topmost 5 bits
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bics r1, r1, #0xf8000000
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bne 3f
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.endif
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@ keep track of the checked GPR
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mov r1, #4
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.macro check_reg reg1, reg2=
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ldrd r2, r3, [r12], #8
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eors r2, r2, \reg1
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bne 2f
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add r1, r1, #1
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.ifnb \reg2
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eors r3, r3, \reg2
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bne 2f
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.endif
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add r1, r1, #1
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.endm
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check_reg r4, r5
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check_reg r6, r7
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@ r9 is a volatile register in the ios ABI
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#ifdef __APPLE__
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check_reg r8
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#else
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check_reg r8, r9
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#endif
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check_reg r10, r11
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.purgem check_reg
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b 0f
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4:
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movrel r0, error_message_vfp
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b 1f
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3:
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movrel r0, error_message_fpscr
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b 1f
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2:
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movrel r0, error_message_gpr
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1:
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blx X(checkasm_fail_func)
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0:
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pop {r0, r1}
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.ifc \variant, vfp
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pop {r2}
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fmxr FPSCR, r2
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vpop {d8-d15}
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.endif
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pop {r4-r11, pc}
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endfunc
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.endm
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#if HAVE_VFP || HAVE_NEON
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clobbercheck vfp
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#endif
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clobbercheck novfp
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