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f399e406af
Implicit vector loads on POWER7 hardware can use the VSX instruction set instead of classic Altivec/VMX. Let's force a VMX load in this case. Signed-off-by: Martin Storsjö <martin@martin.st>
144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/*
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* Copyright (c) 2007 Luca Barbato <lu_zero@gentoo.org>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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** @file
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** integer misc ops.
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**/
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#include "config.h"
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#if HAVE_ALTIVEC_H
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#include <altivec.h>
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#endif
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#include "libavutil/attributes.h"
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#include "libavutil/ppc/types_altivec.h"
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#include "libavcodec/dsputil.h"
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#include "dsputil_altivec.h"
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static int ssd_int8_vs_int16_altivec(const int8_t *pix1, const int16_t *pix2,
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int size) {
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int i, size16;
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vector signed char vpix1;
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vector signed short vpix2, vdiff, vpix1l,vpix1h;
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union { vector signed int vscore;
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int32_t score[4];
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} u;
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u.vscore = vec_splat_s32(0);
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//
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//XXX lazy way, fix it later
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#define vec_unaligned_load(b) \
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vec_perm(vec_ld(0,b),vec_ld(15,b),vec_lvsl(0, b));
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size16 = size >> 4;
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while(size16) {
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// score += (pix1[i]-pix2[i])*(pix1[i]-pix2[i]);
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//load pix1 and the first batch of pix2
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vpix1 = vec_unaligned_load(pix1);
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vpix2 = vec_unaligned_load(pix2);
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pix2 += 8;
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//unpack
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vpix1h = vec_unpackh(vpix1);
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vdiff = vec_sub(vpix1h, vpix2);
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vpix1l = vec_unpackl(vpix1);
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// load another batch from pix2
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vpix2 = vec_unaligned_load(pix2);
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u.vscore = vec_msum(vdiff, vdiff, u.vscore);
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vdiff = vec_sub(vpix1l, vpix2);
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u.vscore = vec_msum(vdiff, vdiff, u.vscore);
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pix1 += 16;
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pix2 += 8;
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size16--;
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}
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u.vscore = vec_sums(u.vscore, vec_splat_s32(0));
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size %= 16;
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for (i = 0; i < size; i++) {
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u.score[3] += (pix1[i]-pix2[i])*(pix1[i]-pix2[i]);
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}
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return u.score[3];
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}
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static int32_t scalarproduct_int16_altivec(const int16_t *v1, const int16_t *v2,
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int order)
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{
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int i;
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LOAD_ZERO;
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register vec_s16 vec1;
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register vec_s32 res = vec_splat_s32(0), t;
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int32_t ires;
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for(i = 0; i < order; i += 8){
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vec1 = vec_unaligned_load(v1);
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t = vec_msum(vec1, vec_ld(0, v2), zero_s32v);
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res = vec_sums(t, res);
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v1 += 8;
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v2 += 8;
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}
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res = vec_splat(res, 3);
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vec_ste(res, 0, &ires);
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return ires;
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}
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static int32_t scalarproduct_and_madd_int16_altivec(int16_t *v1, const int16_t *v2, const int16_t *v3, int order, int mul)
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{
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LOAD_ZERO;
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vec_s16 *pv1 = (vec_s16*)v1;
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register vec_s16 muls = {mul,mul,mul,mul,mul,mul,mul,mul};
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register vec_s16 t0, t1, i0, i1, i4;
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register vec_s16 i2 = vec_ld(0, v2), i3 = vec_ld(0, v3);
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register vec_s32 res = zero_s32v;
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register vec_u8 align = vec_lvsl(0, v2);
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int32_t ires;
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order >>= 4;
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do {
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i1 = vec_ld(16, v2);
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t0 = vec_perm(i2, i1, align);
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i2 = vec_ld(32, v2);
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t1 = vec_perm(i1, i2, align);
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i0 = pv1[0];
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i1 = pv1[1];
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res = vec_msum(t0, i0, res);
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res = vec_msum(t1, i1, res);
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i4 = vec_ld(16, v3);
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t0 = vec_perm(i3, i4, align);
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i3 = vec_ld(32, v3);
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t1 = vec_perm(i4, i3, align);
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pv1[0] = vec_mladd(t0, muls, i0);
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pv1[1] = vec_mladd(t1, muls, i1);
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pv1 += 2;
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v2 += 16;
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v3 += 16;
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} while(--order);
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res = vec_splat(vec_sums(res, zero_s32v), 3);
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vec_ste(res, 0, &ires);
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return ires;
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}
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av_cold void ff_int_init_altivec(DSPContext *c, AVCodecContext *avctx)
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{
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c->ssd_int8_vs_int16 = ssd_int8_vs_int16_altivec;
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c->scalarproduct_int16 = scalarproduct_int16_altivec;
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c->scalarproduct_and_madd_int16 = scalarproduct_and_madd_int16_altivec;
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}
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