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Add extension to use interrupt.

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This commit is contained in:
Andrew Walbran 2023-04-12 16:32:03 +01:00
parent 8cdb93cc74
commit 3b22bb5625
2 changed files with 6 additions and 3 deletions
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4
src/exercises/bare-metal/rtc.md
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@ -7,6 +7,8 @@ should write a driver for it.
date/time formatting. date/time formatting.
2. Use the match register and raw interrupt status to busy-wait until a given time, e.g. 3 seconds 2. Use the match register and raw interrupt status to busy-wait until a given time, e.g. 3 seconds
in the future. (Call [`core::hint::spin_loop`][3] inside the loop.) in the future. (Call [`core::hint::spin_loop`][3] inside the loop.)
3. _Extension if you have time:_ Enable and handle the interrupt generated by the RTC match. You can
use the driver provided in the `gicv3` module to configure the Arm Generic Interrupt Controller.
Download the [exercise template](../../comprehensive-rust-exercises.zip) and look in the `rtc` Download the [exercise template](../../comprehensive-rust-exercises.zip) and look in the `rtc`
directory for the following files. directory for the following files.
@ -29,7 +31,7 @@ directory for the following files.
{{#include rtc/src/main.rs:main_end}} {{#include rtc/src/main.rs:main_end}}
``` ```
`src/exceptions.rs` (you shouldn't need to change this): `src/exceptions.rs` (you should only need to change this for the 3rd part of the exercise):
<!-- File src/exceptions.rs --> <!-- File src/exceptions.rs -->

5
src/exercises/bare-metal/rtc/src/main.rs
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@ -23,11 +23,12 @@ mod pl011;
// ANCHOR_END: top // ANCHOR_END: top
mod pl031; mod pl031;
use crate::gicv3::{irq_enable, wfi, GicV3, IntId, Trigger}; use crate::gicv3::{irq_enable, wfi, IntId, Trigger};
use crate::pl031::Rtc; use crate::pl031::Rtc;
use chrono::{TimeZone, Utc}; use chrono::{TimeZone, Utc};
use core::hint::spin_loop; use core::hint::spin_loop;
// ANCHOR: imports // ANCHOR: imports
use crate::gicv3::GicV3;
use crate::pl011::Uart; use crate::pl011::Uart;
use core::panic::PanicInfo; use core::panic::PanicInfo;
use log::{error, info, trace, LevelFilter}; use log::{error, info, trace, LevelFilter};
@ -55,13 +56,13 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
logger::init(uart, LevelFilter::Trace).unwrap(); logger::init(uart, LevelFilter::Trace).unwrap();
info!("main({:#x}, {:#x}, {:#x}, {:#x})", x0, x1, x2, x3); info!("main({:#x}, {:#x}, {:#x}, {:#x})", x0, x1, x2, x3);
// ANCHOR_END: main
// Safe because `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base // Safe because `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base
// addresses of a GICv3 distributor and redistributor respectively, and // addresses of a GICv3 distributor and redistributor respectively, and
// nothing else accesses those address ranges. // nothing else accesses those address ranges.
let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS) }; let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS) };
gic.setup(); gic.setup();
// ANCHOR_END: main
// Safe because `PL031_BASE_ADDRESS` is the base address of a PL031 device, // Safe because `PL031_BASE_ADDRESS` is the base address of a PL031 device,
// and nothing else accesses that address range. // and nothing else accesses that address range.