rust/comprehensive-rust
1
0
Fork 0
mirror of https://github.com/google/comprehensive-rust.git synced 2025-04-05 01:55:31 +02:00
Code Issues Releases Activity

Try sending an SGI.

Browse Source
This commit is contained in:
Andrew Walbran 2023-04-12 16:33:39 +01:00
parent 3e4a869587
commit dc65f68391
2 changed files with 47 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/exercises/bare-metal/rtc/src/gicv3.rs
View File

@ -466,6 +466,22 @@ impl GicV3 {
}
}
pub fn gicd_pending(&self, index: usize) -> u32 {
unsafe { addr_of!((*self.gicd).ispendr[index]).read_volatile() }
}
pub fn gicr_pending(&self) -> u32 {
unsafe { addr_of!((*self.sgi).ispendr0).read_volatile() }
}
pub fn gicd_active(&self, index: usize) -> u32 {
unsafe { addr_of!((*self.gicd).isactiver[index]).read_volatile() }
}
pub fn gicr_active(&self) -> u32 {
unsafe { addr_of!((*self.sgi).isactiver0).read_volatile() }
}
/// Enables or disables the interrupt with the given ID.
pub fn enable_interrupt(&mut self, intid: IntId, enable: bool) {
let index = (intid.0 / 32) as usize;

32
src/exercises/bare-metal/rtc/src/main.rs
View File

@ -23,7 +23,7 @@ mod pl011;
// ANCHOR_END: top
mod pl031;
use crate::gicv3::{irq_enable, wfi, IntId, Trigger};
use crate::gicv3::{irq_enable, wfi, IntId, SgiTarget, Trigger};
use crate::pl031::Rtc;
use chrono::{TimeZone, Utc};
use core::hint::spin_loop;
@ -64,6 +64,36 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
gic.setup();
// ANCHOR_END: main
// Test sending an SGI.
let sgi_intid = IntId::sgi(3);
GicV3::set_priority_mask(0xff);
gic.set_interrupt_priority(sgi_intid, 0x80);
irq_enable();
gic.enable_interrupt(sgi_intid, true);
assert_eq!(gic.gicd_pending(0), 0);
assert_eq!(gic.gicr_pending(), 0);
assert_eq!(gic.gicd_active(0), 0);
assert_eq!(gic.gicr_active(), 0);
info!("Sending SGI");
GicV3::send_sgi(
sgi_intid,
SgiTarget::List {
affinity3: 0,
affinity2: 0,
affinity1: 0,
target_list: 0b1,
},
);
info!("Sent SGI");
assert_eq!(gic.gicd_pending(0), 0);
assert_eq!(gic.gicr_pending(), 0);
assert_eq!(gic.gicd_active(0), 0);
assert_eq!(gic.gicr_active(), 0);
loop {
wfi();
}
// Safe because `PL031_BASE_ADDRESS` is the base address of a PL031 device,
// and nothing else accesses that address range.
let mut rtc = unsafe { Rtc::new(PL031_BASE_ADDRESS) };