virtualenv/FFmpeg
1
0
Fork 0
mirror of https://github.com/FFmpeg/FFmpeg.git synced 2024-12-12 19:18:44 +02:00
Code Issues Releases Activity
9fd88bd092
FFmpeg/libavcodec/riscv/flacdsp_rvv.S

609 lines
15 KiB
ArmAsm
Raw Normal View History

lavc/flacdsp: R-V V packed decorrelate_{l,r}s flac_decorrelate_ms_16_c: 457.2 flac_decorrelate_ms_16_rvv_i32: 203.0 flac_decorrelate_ms_32_c: 457.2 flac_decorrelate_ms_32_rvv_i32: 203.5 flac_decorrelate_rs_16_c: 456.2 flac_decorrelate_rs_16_rvv_i32: 207.0 flac_decorrelate_rs_32_c: 456.2 flac_decorrelate_rs_32_rvv_i32: 210.5
2023-08-16 20:29:10 +02:00
/*
* Copyright © 2023 Rémi Denis-Courmont.
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "libavutil/riscv/asm.S"
lavc/flacdsp: optimise RVV vector type for lpc16 This calculates the optimal vector type value at run-time based on the hardware vector length and the FLAC LPC prediction order. In this particular case, the additional computation is easily amortised over the loop iterations: T-Head C908: C V before V after 1 48.0 214.7 95.2 2 64.7 214.2 94.7 3 79.7 213.5 94.5 4 96.2 196.5 94.2 # 5 111.0 195.7 118.5 6 127.0 211.2 102.0 7 143.7 194.2 101.5 8 175.7 193.2 101.2 # 9 176.2 224.2 126.0 10 191.5 192.0 125.5 11 224.5 191.2 124.7 12 223.0 190.2 124.2 13 239.2 189.5 123.7 14 253.7 188.7 139.5 15 286.2 188.0 122.7 16 284.0 187.0 122.5 # 17 300.2 186.5 186.5 18 314.0 185.5 185.7 19 329.7 184.7 185.0 20 343.0 184.2 184.2 21 358.7 199.2 183.7 22 371.7 182.7 182.7 23 387.5 181.7 182.0 24 400.7 181.0 181.2 25 431.5 180.2 196.5 26 443.7 195.5 196.0 27 459.0 178.7 196.2 28 470.7 177.7 194.2 29 470.0 177.0 193.5 30 481.2 176.2 176.5 31 496.2 175.5 175.7 32 507.2 174.7 191.0 # # Power of two boundary. With 128-bit vectors, improvements are expected for the first two test cases only. For the other two, there is overhead but below noise. Improvements should be better observable with prediction order of 8 and less, or on hardware with larger vector sizes.
2024-05-14 21:15:43 +02:00
func ff_flac_lpc16_rvv, zve32x, zbb
vtype_vli t0, a2, t2, e32, ta, ma
vsetvl zero, a2, t0
lavc/flacdsp: R-V V LPC16 function In this case, the inner loop computing the scalar product can be reduced to just one multiplication and one sum even with 128-bit vectors. The result is a lot simpler, but also brings more modest performance gains: flac_lpc_16_13_c: 15241.0 flac_lpc_16_13_rvv_i32: 11230.0 flac_lpc_16_16_c: 17884.0 flac_lpc_16_16_rvv_i32: 12125.7 flac_lpc_16_29_c: 27847.7 flac_lpc_16_29_rvv_i32: 10494.0 flac_lpc_16_32_c: 30051.5 flac_lpc_16_32_rvv_i32: 10355.0
2023-11-15 21:31:17 +02:00
vle32.v v8, (a1)
sub a4, a4, a2
vle32.v v16, (a0)
sh2add a0, a2, a0
vmv.s.x v0, zero
1:
vmul.vv v24, v8, v16
lw t0, (a0)
vredsum.vs v24, v24, v0
addi a4, a4, -1
vmv.x.s t1, v24
sra t1, t1, a3
add t0, t0, t1
vslide1down.vx v16, v16, t0
sw t0, (a0)
addi a0, a0, 4
bnez a4, 1b
ret
endfunc
lavc/flacdsp: R-V V packed decorrelate_{l,r}s flac_decorrelate_ms_16_c: 457.2 flac_decorrelate_ms_16_rvv_i32: 203.0 flac_decorrelate_ms_32_c: 457.2 flac_decorrelate_ms_32_rvv_i32: 203.5 flac_decorrelate_rs_16_c: 456.2 flac_decorrelate_rs_16_rvv_i32: 207.0 flac_decorrelate_rs_32_c: 456.2 flac_decorrelate_rs_32_rvv_i32: 210.5
2023-08-16 20:29:10 +02:00
#if (__riscv_xlen == 64)
lavc/flacdsp: fix CPU requirement for 32-bit LPC
2024-05-13 17:51:38 +02:00
func ff_flac_lpc32_rvv, zve64x
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
addi t2, a2, -16
ble t2, zero, ff_flac_lpc32_rvv_simple
vsetivli zero, 1, e64, m1, ta, ma
vmv.s.x v0, zero
vsetvli zero, a2, e32, m8, ta, ma
vle32.v v8, (a1)
sub a4, a4, a2
vle32.v v16, (a0)
sh2add a0, a2, a0
1:
lavc/flacdsp: do not assume maximum R-V VL This loop correctly assumes that VLMAX=16 (4x128-bit vectors with 32-bit elements) and 32 >= pred_order > 16. We need to alternate between VL=16 and VL=t2=pred_order-16 elements to add up to pred_order. The current code requests AVL=a2=pred_order elements. In QEMU and on thte K230 hardware, this sets VL=16 as we need. But the specification merely guarantees that we get: ceil(AVL / 2) <= VL <= VLMAX. For instance, if pred_order equals 27, we could end up with VL=14 or VL=15 instead of VL=16. So instead, request literally VLMAX=16.
2024-05-24 19:17:10 +02:00
vsetvli t1, zero, e32, m4, ta, ma
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
vwmul.vv v24, v8, v16
vsetvli zero, t2, e32, m4, tu, ma
vwmacc.vv v24, v12, v20
lavc/flacdsp: do not assume maximum R-V VL This loop correctly assumes that VLMAX=16 (4x128-bit vectors with 32-bit elements) and 32 >= pred_order > 16. We need to alternate between VL=16 and VL=t2=pred_order-16 elements to add up to pred_order. The current code requests AVL=a2=pred_order elements. In QEMU and on thte K230 hardware, this sets VL=16 as we need. But the specification merely guarantees that we get: ceil(AVL / 2) <= VL <= VLMAX. For instance, if pred_order equals 27, we could end up with VL=14 or VL=15 instead of VL=16. So instead, request literally VLMAX=16.
2024-05-24 19:17:10 +02:00
vsetvli t1, zero, e64, m8, ta, ma
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
vredsum.vs v24, v24, v0
lw t0, (a0)
addi a4, a4, -1
vmv.x.s t1, v24
vsetvli zero, a2, e32, m8, ta, ma
sra t1, t1, a3
add t0, t0, t1
vslide1down.vx v16, v16, t0
sw t0, (a0)
addi a0, a0, 4
bnez a4, 1b
ret
endfunc
lavc/flacdsp: optimise RVV vector type for lpc32 This is pretty much the same as for lpc16, though it only improves half as large prediction orders. With 128-bit vectors, this gives: C V old V new 1 69.2 181.5 95.5 2 107.7 180.7 95.2 3 145.5 180.0 103.5 4 183.0 179.2 102.7 5 220.7 178.5 128.0 6 257.7 194.0 127.5 7 294.5 193.7 126.7 8 331.0 193.0 126.5 Larger prediction orders see no significant changes at that size.
2024-05-15 21:56:42 +02:00
func ff_flac_lpc32_rvv_simple, zve64x, zbb
vtype_vli t3, a2, t1, e64, ta, ma
vntypei t2, t3
vsetvl zero, a2, t3 // e64
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
vmv.s.x v0, zero
lavc/flacdsp: optimise RVV vector type for lpc32 This is pretty much the same as for lpc16, though it only improves half as large prediction orders. With 128-bit vectors, this gives: C V old V new 1 69.2 181.5 95.5 2 107.7 180.7 95.2 3 145.5 180.0 103.5 4 183.0 179.2 102.7 5 220.7 178.5 128.0 6 257.7 194.0 127.5 7 294.5 193.7 126.7 8 331.0 193.0 126.5 Larger prediction orders see no significant changes at that size.
2024-05-15 21:56:42 +02:00
vsetvl zero, zero, t2 // e32
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
vle32.v v8, (a1)
sub a4, a4, a2
vle32.v v16, (a0)
sh2add a0, a2, a0
1:
vwmul.vv v24, v8, v16
lavc/flacdsp: optimise RVV vector type for lpc32 This is pretty much the same as for lpc16, though it only improves half as large prediction orders. With 128-bit vectors, this gives: C V old V new 1 69.2 181.5 95.5 2 107.7 180.7 95.2 3 145.5 180.0 103.5 4 183.0 179.2 102.7 5 220.7 178.5 128.0 6 257.7 194.0 127.5 7 294.5 193.7 126.7 8 331.0 193.0 126.5 Larger prediction orders see no significant changes at that size.
2024-05-15 21:56:42 +02:00
vsetvl zero, zero, t3 // e64
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
vredsum.vs v24, v24, v0
lw t0, (a0)
addi a4, a4, -1
vmv.x.s t1, v24
lavc/flacdsp: optimise RVV vector type for lpc32 This is pretty much the same as for lpc16, though it only improves half as large prediction orders. With 128-bit vectors, this gives: C V old V new 1 69.2 181.5 95.5 2 107.7 180.7 95.2 3 145.5 180.0 103.5 4 183.0 179.2 102.7 5 220.7 178.5 128.0 6 257.7 194.0 127.5 7 294.5 193.7 126.7 8 331.0 193.0 126.5 Larger prediction orders see no significant changes at that size.
2024-05-15 21:56:42 +02:00
vsetvl zero, zero, t2 // e32
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
sra t1, t1, a3
add t0, t0, t1
vslide1down.vx v16, v16, t0
sw t0, (a0)
addi a0, a0, 4
bnez a4, 1b
ret
endfunc
lavc/flacdsp: R-V Zvl256b lpc33 flac_lpc_33_13_c: 499.7 flac_lpc_33_13_rvv_i64: 197.7 flac_lpc_33_16_c: 601.5 flac_lpc_33_16_rvv_i64: 195.2 flac_lpc_33_29_c: 1011.5 flac_lpc_33_29_rvv_i64: 300.7 flac_lpc_33_32_c: 1099.0 flac_lpc_33_32_rvv_i64: 296.7
2024-05-13 22:20:46 +02:00
func ff_flac_lpc33_rvv, zve64x, zbb
vtype_vli t0, a3, t1, e64, ta, ma
vsetvl zero, a3, t0
vmv.s.x v0, zero
sh2add a1, a3, a1
vle32.v v24, (a2)
sub a5, a5, a3
vle64.v v16, (a0)
sh3add a0, a3, a0
vsext.vf2 v8, v24
1:
vmul.vv v24, v8, v16
lw t0, (a1)
addi a1, a1, 4
vredsum.vs v24, v24, v0
addi a5, a5, -1
vmv.x.s t1, v24
sra t1, t1, a4
add t0, t0, t1
vslide1down.vx v16, v16, t0
sd t0, (a0)
addi a0, a0, 8
bnez a5, 1b
ret
endfunc
lavc/flacdsp: R-V V flac_wasted32 T-Head C908: flac_wasted_32_c: 949.0 flac_wasted_32_rvv_i32: 278.7
2024-05-12 18:40:30 +02:00
#endif
lavc/flacdsp: R-V V LPC32 The entire set of 32 coefficients and corresponding past 32 samples can fit in a single vector (with LMUL=8) exactly, but... since widening double the needed vector sizes, we still end up too short with 128-bit vectors. This adds a very simple version for future 256+-bit hardware, and for pred_orders values up to 16, and a bit more involved loop for for 128-bit hardware with pred_orders between 17 and 32. With 128-bit hardware, the benchmarks look like this: flac_lpc_32_13_c: 30152.0 flac_lpc_32_13_rvv_i32: 10244.7 flac_lpc_32_16_c: 37314.2 flac_lpc_32_16_rvv_i32: 10126.2 flac_lpc_32_29_c: 61910.0 flac_lpc_32_29_rvv_i32: 14495.2 flac_lpc_32_32_c: 68204.0 flac_lpc_32_32_rvv_i32: 13273.7
2023-11-15 19:46:18 +02:00
lavc/flacdsp: R-V V flac_wasted32 T-Head C908: flac_wasted_32_c: 949.0 flac_wasted_32_rvv_i32: 278.7
2024-05-12 18:40:30 +02:00
func ff_flac_wasted32_rvv, zve32x
1:
vsetvli t0, a2, e32, m8, ta, ma
vle32.v v8, (a0)
sub a2, a2, t0
vsll.vx v8, v8, a1
vse32.v v8, (a0)
sh2add a0, t0, a0
bnez a2, 1b
ret
endfunc
lavc/flacdsp: R-V V flac_wasted33 T-Head C908: flac_wasted_33_c: 786.2 flac_wasted_33_rvv_i64: 486.5
2024-05-12 19:02:03 +02:00
func ff_flac_wasted33_rvv, zve64x
srli t0, a2, 5
li t1, 1
bnez t0, 2f
sll a2, t1, a2
1:
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v8, (a1)
sub a3, a3, t0
vwmulsu.vx v16, v8, a2
sh2add a1, t0, a1
vse64.v v16, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
2: // Pessimistic case: wasted >= 32
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v8, (a1)
sub a3, a3, t0
vwcvtu.x.x.v v16, v8
sh2add a1, t0, a1
vsetvli zero, zero, e64, m8, ta, ma
vsll.vx v16, v16, a2
vse64.v v16, (a0)
sh3add a0, t0, a0
bnez a3, 2b
ret
endfunc
lavc/flacdsp: R-V V flac_wasted32 T-Head C908: flac_wasted_32_c: 949.0 flac_wasted_32_rvv_i32: 278.7
2024-05-12 18:40:30 +02:00
#if (__riscv_xlen == 64)
lavc/flacdsp: R-V V decorrelate_indep 16-bit packed flac_decorrelate_indep2_16_c: 981.7 flac_decorrelate_indep2_16_rvv_i32: 199.2 flac_decorrelate_indep4_16_c: 1749.7 flac_decorrelate_indep4_16_rvv_i32: 401.2 flac_decorrelate_indep6_16_c: 2517.7 flac_decorrelate_indep6_16_rvv_i32: 858.0 flac_decorrelate_indep8_16_c: 3285.7 flac_decorrelate_indep8_16_rvv_i32: 1123.5
2023-11-14 23:13:34 +02:00
func ff_flac_decorrelate_indep2_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m8, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v8, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vsll.vx v8, v8, a4
vsetvli zero, zero, e16, m4, ta, ma
vncvt.x.x.w v16, v0
vncvt.x.x.w v20, v8
vsseg2e16.v v16, (a0)
sh2add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_indep4_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld t1, 16(a1)
ld t2, 24(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v4, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vle32.v v8, (t1)
sh2add t1, t0, t1
vsll.vx v4, v4, a4
vle32.v v12, (t2)
sh2add t2, t0, t2
vsll.vx v8, v8, a4
vsll.vx v12, v12, a4
vsetvli zero, zero, e16, m2, ta, ma
vncvt.x.x.w v16, v0
vncvt.x.x.w v18, v4
vncvt.x.x.w v20, v8
vncvt.x.x.w v22, v12
vsseg4e16.v v16, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_indep6_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld t1, 16(a1)
ld t2, 24(a1)
ld t3, 32(a1)
ld t4, 40(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m2, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v2, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vle32.v v4, (t1)
sh2add t1, t0, t1
vsll.vx v2, v2, a4
vle32.v v6, (t2)
sh2add t2, t0, t2
vsll.vx v4, v4, a4
vle32.v v8, (t3)
sh2add t3, t0, t3
vsll.vx v6, v6, a4
vle32.v v10, (t4)
sh2add t4, t0, t4
vsll.vx v8, v8, a4
slli t0, t0, 2
vsll.vx v10, v10, a4
sh1add t0, t0, t0 // t0 *= 3
vsetvli zero, zero, e16, m1, ta, ma
vncvt.x.x.w v16, v0
vncvt.x.x.w v17, v2
vncvt.x.x.w v18, v4
vncvt.x.x.w v19, v6
vncvt.x.x.w v20, v8
vncvt.x.x.w v21, v10
vsseg6e16.v v16, (a0)
add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_indep8_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld t1, 16(a1)
ld t2, 24(a1)
ld t3, 32(a1)
ld t4, 40(a1)
ld t5, 48(a1)
ld t6, 56(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m2, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v2, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
vle32.v v4, (t1)
sh2add a2, t0, a2
vsll.vx v2, v2, a4
sh2add t1, t0, t1
vle32.v v6, (t2)
vsll.vx v4, v4, a4
sh2add t2, t0, t2
vle32.v v8, (t3)
sh2add t3, t0, t3
vsll.vx v6, v6, a4
vle32.v v10, (t4)
sh2add t4, t0, t4
vsll.vx v8, v8, a4
vle32.v v12, (t5)
sh2add t5, t0, t5
vsll.vx v10, v10, a4
vle32.v v14, (t6)
sh2add t6, t0, t6
vsll.vx v12, v12, a4
slli t0, t0, 4
vsll.vx v14, v14, a4
vsetvli zero, zero, e16, m1, ta, ma
vncvt.x.x.w v16, v0
vncvt.x.x.w v17, v2
vncvt.x.x.w v18, v4
vncvt.x.x.w v19, v6
vncvt.x.x.w v20, v8
vncvt.x.x.w v21, v10
vncvt.x.x.w v22, v12
vncvt.x.x.w v23, v14
vsseg8e16.v v16, (a0)
add a0, t0, a0
bnez a3, 1b
ret
endfunc
lavc/flacdsp: R-V V packed decorrelate_{l,r}s flac_decorrelate_ms_16_c: 457.2 flac_decorrelate_ms_16_rvv_i32: 203.0 flac_decorrelate_ms_32_c: 457.2 flac_decorrelate_ms_32_rvv_i32: 203.5 flac_decorrelate_rs_16_c: 456.2 flac_decorrelate_rs_16_rvv_i32: 207.0 flac_decorrelate_rs_32_c: 456.2 flac_decorrelate_rs_32_rvv_i32: 210.5
2023-08-16 20:29:10 +02:00
func ff_flac_decorrelate_ls_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m8, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v8, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vsll.vx v8, v8, a4
vsub.vv v8, v0, v8
vsetvli zero, zero, e16, m4, ta, ma
vncvt.x.x.w v16, v0
vncvt.x.x.w v20, v8
vsseg2e16.v v16, (a0)
sh2add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_rs_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m8, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v8, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vsll.vx v8, v8, a4
vadd.vv v0, v0, v8
vsetvli zero, zero, e16, m4, ta, ma
vncvt.x.x.w v16, v0
vncvt.x.x.w v20, v8
vsseg2e16.v v16, (a0)
sh2add a0, t0, a0
bnez a3, 1b
ret
endfunc
lavc/flacdsp: R-V V decorrelate_ms packed flac_decorrelate_ms_16_c: 585.5 flac_decorrelate_ms_16_rvv_i32: 263.0 flac_decorrelate_ms_32_c: 584.7 flac_decorrelate_ms_32_rvv_i32: 250.0
2023-11-13 21:46:16 +02:00
func ff_flac_decorrelate_ms_16_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m8, ta, ma
vle32.v v8, (a2)
sub a3, a3, t0
vle32.v v0, (a1)
sh2add a1, t0, a1
vsra.vi v16, v8, 1
sh2add a2, t0, a2
vsub.vv v24, v0, v16
vadd.vv v16, v24, v8
vsll.vx v8, v24, a4
vsll.vx v0, v16, a4
vsetvli zero, zero, e16, m4, ta, ma
vncvt.x.x.w v0, v0
vncvt.x.x.w v4, v8
vsseg2e16.v v0, (a0)
sh2add a0, t0, a0
bnez a3, 1b
ret
endfunc
lavc/flacdsp: R-V V decorrelate_indep 32-bit packed flac_decorrelate_indep2_32_c: 981.7 flac_decorrelate_indep2_32_rvv_i32: 183.7 flac_decorrelate_indep4_32_c: 1749.7 flac_decorrelate_indep4_32_rvv_i32: 362.5 flac_decorrelate_indep6_32_c: 2517.7 flac_decorrelate_indep6_32_rvv_i32: 715.2 flac_decorrelate_indep8_32_c: 3285.7 flac_decorrelate_indep8_32_rvv_i32: 909.0
2023-11-14 20:28:45 +02:00
func ff_flac_decorrelate_indep2_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v4, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vsll.vx v4, v4, a4
vsseg2e32.v v0, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_indep4_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld t1, 16(a1)
ld t2, 24(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m2, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v2, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vle32.v v4, (t1)
sh2add t1, t0, t1
vsll.vx v2, v2, a4
vle32.v v6, (t2)
sh2add t2, t0, t2
vsll.vx v4, v4, a4
slli t0, t0, 4
vsll.vx v6, v6, a4
vsseg4e32.v v0, (a0)
add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_indep6_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld t1, 16(a1)
ld t2, 24(a1)
ld t3, 32(a1)
ld t4, 40(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m1, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v1, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vle32.v v2, (t1)
sh2add t1, t0, t1
vsll.vx v1, v1, a4
vle32.v v3, (t2)
sh2add t2, t0, t2
vsll.vx v2, v2, a4
vle32.v v4, (t3)
sh2add t3, t0, t3
vsll.vx v3, v3, a4
vle32.v v5, (t4)
sh2add t4, t0, t4
vsll.vx v4, v4, a4
slli t0, t0, 3
vsll.vx v5, v5, a4
sh1add t0, t0, t0 // t0 *= 3
vsseg6e32.v v0, (a0)
add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_indep8_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld t1, 16(a1)
ld t2, 24(a1)
ld t3, 32(a1)
ld t4, 40(a1)
ld t5, 48(a1)
ld t6, 56(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m1, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v1, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
vle32.v v2, (t1)
sh2add a2, t0, a2
vsll.vx v1, v1, a4
sh2add t1, t0, t1
vle32.v v3, (t2)
vsll.vx v2, v2, a4
sh2add t2, t0, t2
vle32.v v4, (t3)
sh2add t3, t0, t3
vsll.vx v3, v3, a4
vle32.v v5, (t4)
sh2add t4, t0, t4
vsll.vx v4, v4, a4
vle32.v v6, (t5)
sh2add t5, t0, t5
vsll.vx v5, v5, a4
vle32.v v7, (t6)
sh2add t6, t0, t6
vsll.vx v6, v6, a4
slli t0, t0, 5
vsll.vx v7, v7, a4
vsseg8e32.v v0, (a0)
add a0, t0, a0
bnez a3, 1b
ret
endfunc
lavc/flacdsp: R-V V packed decorrelate_{l,r}s flac_decorrelate_ms_16_c: 457.2 flac_decorrelate_ms_16_rvv_i32: 203.0 flac_decorrelate_ms_32_c: 457.2 flac_decorrelate_ms_32_rvv_i32: 203.5 flac_decorrelate_rs_16_c: 456.2 flac_decorrelate_rs_16_rvv_i32: 207.0 flac_decorrelate_rs_32_c: 456.2 flac_decorrelate_rs_32_rvv_i32: 210.5
2023-08-16 20:29:10 +02:00
func ff_flac_decorrelate_ls_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v4, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vsll.vx v4, v4, a4
vsub.vv v4, v0, v4
vsseg2e32.v v0, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc
func ff_flac_decorrelate_rs_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v0, (a1)
sub a3, a3, t0
vle32.v v4, (a2)
sh2add a1, t0, a1
vsll.vx v0, v0, a4
sh2add a2, t0, a2
vsll.vx v4, v4, a4
vadd.vv v0, v0, v4
vsseg2e32.v v0, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc
lavc/flacdsp: R-V V decorrelate_ms packed flac_decorrelate_ms_16_c: 585.5 flac_decorrelate_ms_16_rvv_i32: 263.0 flac_decorrelate_ms_32_c: 584.7 flac_decorrelate_ms_32_rvv_i32: 250.0
2023-11-13 21:46:16 +02:00
func ff_flac_decorrelate_ms_32_rvv, zve32x
ld a0, (a0)
ld a2, 8(a1)
ld a1, (a1)
1:
vsetvli t0, a3, e32, m4, ta, ma
vle32.v v4, (a2)
sub a3, a3, t0
vle32.v v0, (a1)
sh2add a1, t0, a1
vsra.vi v8, v4, 1
sh2add a2, t0, a2
vsub.vv v12, v0, v8
vadd.vv v8, v12, v4
vsll.vx v4, v12, a4
vsll.vx v0, v8, a4
vsseg2e32.v v0, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc
lavc/flacdsp: R-V V packed decorrelate_{l,r}s flac_decorrelate_ms_16_c: 457.2 flac_decorrelate_ms_16_rvv_i32: 203.0 flac_decorrelate_ms_32_c: 457.2 flac_decorrelate_ms_32_rvv_i32: 203.5 flac_decorrelate_rs_16_c: 456.2 flac_decorrelate_rs_16_rvv_i32: 207.0 flac_decorrelate_rs_32_c: 456.2 flac_decorrelate_rs_32_rvv_i32: 210.5
2023-08-16 20:29:10 +02:00
#endif
Reference in New Issue Copy Permalink