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vp9: refactor 10/12bpp dc-only code in 4x4/8x8 and add to 16x16.
This commit is contained in:
Ronald S. Bultje
parent
1338fb79d4
commit
0e80265b0a
@ -186,6 +186,17 @@ IWHT4_FN 12, 4095
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VP9_STORE_2X 2, 3, 6, 7, 4, 5
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%endmacro
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%macro DC_ONLY 2 ; shift, zero
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mov coefd, dword [blockq]
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movd [blockq], %2
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imul coefd, 11585
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add coefd, 8192
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sar coefd, 14
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imul coefd, 11585
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add coefd, ((1 << (%1 - 1)) << 14) + 8192
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sar coefd, 14 + %1
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%endmacro
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; 4x4 coefficients are 5+depth+sign bits, so for 10bpp, everything still fits
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; in 15+1 words without additional effort, since the coefficients are 15bpp.
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@ -195,26 +206,20 @@ cglobal vp9_idct_idct_4x4_add_10, 4, 4, 8, dst, stride, block, eob
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jg .idctfull
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; dc-only
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pxor m4, m4
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%if cpuflag(ssse3)
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movd m0, [blockq]
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movd [blockq], m4
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mova m5, [pw_11585x2]
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pmulhrsw m0, m5
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pmulhrsw m0, m5
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%else
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DEFINE_ARGS dst, stride, block, coef
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mov coefd, dword [blockq]
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imul coefd, 11585
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add coefd, 8192
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sar coefd, 14
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imul coefd, 11585
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add coefd, (8 << 14) + 8192
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sar coefd, 14 + 4
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DC_ONLY 4, m4
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movd m0, coefd
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%endif
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pshufw m0, m0, 0
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pxor m4, m4
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mova m5, [pw_1023]
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movh [blockq], m4
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%if cpuflag(ssse3)
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pmulhrsw m0, [pw_2048] ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
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%endif
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@ -368,19 +373,12 @@ cglobal vp9_idct_idct_4x4_add_12, 4, 4, 6, dst, stride, block, eob
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; dword. After the final shift (4), the result is 13+sign bits, so we
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; don't need any additional processing to fit it in a word
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DEFINE_ARGS dst, stride, block, coef
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mov coefd, dword [blockq]
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imul coefd, 11585
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add coefd, 8192
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sar coefd, 14
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imul coefd, 11585
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add coefd, (8 << 14) + 8192
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sar coefd, 14 + 4
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pxor m4, m4
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DC_ONLY 4, m4
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movd m0, coefd
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pshuflw m0, m0, q0000
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punpcklqdq m0, m0
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pxor m4, m4
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mova m5, [pw_4095]
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movd [blockq], m4
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DEFINE_ARGS dst, stride, stride3
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lea stride3q, [strideq*3]
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STORE_4x4 1, 3, 0, 0, m4, m5
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@ -559,17 +557,17 @@ IADST4_12BPP_FN iadst, IADST4, iadst, IADST4
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SWAP 0, 5, 4, 6, 2, 7
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%endmacro
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%macro STORE_2x8 5 ; tmp1-2, reg, min, max
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mova m%1, [dstq+strideq*0]
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mova m%2, [dstq+strideq*1]
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%macro STORE_2x8 5-7 dstq, strideq ; tmp1-2, reg, min, max
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mova m%1, [%6+%7*0]
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mova m%2, [%6+%7*1]
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paddw m%1, m%3
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paddw m%2, m%3
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pmaxsw m%1, %4
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pmaxsw m%2, %4
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pminsw m%1, %5
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pminsw m%2, %5
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mova [dstq+strideq*0], m%1
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mova [dstq+strideq*1], m%2
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mova [%6+%7*0], m%1
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mova [%6+%7*1], m%2
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%endmacro
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%macro PRELOAD 2-3
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@ -598,18 +596,11 @@ cglobal vp9_idct_idct_8x8_add_10, 4, 6 + ARCH_X86_64, 10, \
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; coef values are 16+sign bit, and the coef is 14bit, so 30+sign easily
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; fits in 32bit
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DEFINE_ARGS dst, stride, block, coef
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mov coefd, dword [blockq]
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imul coefd, 11585
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add coefd, 8192
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sar coefd, 14
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imul coefd, 11585
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add coefd, (16 << 14) + 8192
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sar coefd, 14 + 5
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pxor m2, m2
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DC_ONLY 5, m2
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movd m1, coefd
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pshuflw m1, m1, q0000
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punpcklqdq m1, m1
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pxor m2, m2
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movd [blockq], m2
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DEFINE_ARGS dst, stride, cnt
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mov cntd, 4
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.loop_dc:
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@ -676,32 +667,19 @@ cglobal vp9_idct_idct_8x8_add_10, 4, 6 + ARCH_X86_64, 10, \
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ZERO_BLOCK blockq-2*mmsize, 32, 8, m6
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RET
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INIT_XMM sse2
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cglobal vp9_idct_idct_8x8_add_12, 4, 6 + ARCH_X86_64, 10, \
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17 * mmsize + 2 * ARCH_X86_32 * mmsize, \
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dst, stride, block, eob
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mova m0, [pw_4095]
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cmp eobd, 1
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jg mangle(private_prefix %+ _ %+ vp9_idct_idct_8x8_add_10 %+ SUFFIX).idctfull
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; dc-only - unfortunately, this one can overflow, since coefs are 18+sign
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; bpp, and 18+14+sign does not fit in 32bit, so we do 2-stage multiplies
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DEFINE_ARGS dst, stride, block, coef, coefl
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%macro DC_ONLY_64BIT 2 ; shift, zero
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%if ARCH_X86_64
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DEFINE_ARGS dst, stride, block, coef
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movsxd coefq, dword [blockq]
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pxor m2, m2
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movd [blockq], m2
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movd [blockq], %2
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imul coefq, 11585
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add coefq, 8192
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sar coefq, 14
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imul coefq, 11585
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add coefq, (16 << 14) + 8192
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sar coefq, 14 + 5
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add coefq, ((1 << (%1 - 1)) << 14) + 8192
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sar coefq, 14 + %1
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%else
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mov coefd, dword [blockq]
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pxor m2, m2
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movd [blockq], m2
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movd [blockq], %2
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DEFINE_ARGS dst, stride, cnt, coef, coefl
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mov cntd, 2
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.loop_dc_calc:
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@ -715,9 +693,24 @@ cglobal vp9_idct_idct_8x8_add_12, 4, 6 + ARCH_X86_64, 10, \
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add coefd, coefld
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dec cntd
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jg .loop_dc_calc
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add coefd, 16
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sar coefd, 5
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add coefd, 1 << (%1 - 1)
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sar coefd, %1
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%endif
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%endmacro
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INIT_XMM sse2
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cglobal vp9_idct_idct_8x8_add_12, 4, 6 + ARCH_X86_64, 10, \
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17 * mmsize + 2 * ARCH_X86_32 * mmsize, \
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dst, stride, block, eob
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mova m0, [pw_4095]
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cmp eobd, 1
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jg mangle(private_prefix %+ _ %+ vp9_idct_idct_8x8_add_10 %+ SUFFIX).idctfull
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; dc-only - unfortunately, this one can overflow, since coefs are 18+sign
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; bpp, and 18+14+sign does not fit in 32bit, so we do 2-stage multiplies
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DEFINE_ARGS dst, stride, block, coef, coefl
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pxor m2, m2
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DC_ONLY_64BIT 5, m2
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movd m1, coefd
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pshuflw m1, m1, q0000
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punpcklqdq m1, m1
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@ -1000,7 +993,24 @@ cglobal vp9_idct_idct_16x16_add_10, 4, 6 + ARCH_X86_64, 16, \
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cmp eobd, 1
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jg .idctfull
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; dc-only
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; dc-only - the 10bit version can be done entirely in 32bit, since the max
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; coef values are 17+sign bit, and the coef is 14bit, so 31+sign easily
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; fits in 32bit
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DEFINE_ARGS dst, stride, block, coef
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pxor m2, m2
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DC_ONLY 6, m2
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movd m1, coefd
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pshuflw m1, m1, q0000
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punpcklqdq m1, m1
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DEFINE_ARGS dst, stride, cnt
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mov cntd, 8
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.loop_dc:
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STORE_2x8 3, 4, 1, m2, m0, dstq, mmsize
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STORE_2x8 3, 4, 1, m2, m0, dstq+strideq, mmsize
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lea dstq, [dstq+strideq*2]
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dec cntd
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jg .loop_dc
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RET
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.idctfull:
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mova [rsp+64*mmsize], m0
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@ -1013,7 +1023,6 @@ cglobal vp9_idct_idct_16x16_add_10, 4, 6 + ARCH_X86_64, 16, \
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mov ptrq, rsp
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.loop_1:
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IDCT16_1D blockq
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; order: 2,1,0,11,3,7,9,10,6,8,4,5,12,13,r65,15
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TRANSPOSE4x4D 0, 1, 2, 3, 7
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mova [ptrq+ 1*mmsize], m0
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@ -1106,6 +1115,20 @@ cglobal vp9_idct_idct_16x16_add_12, 4, 6 + ARCH_X86_64, 16, \
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cmp eobd, 1
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jg mangle(private_prefix %+ _ %+ vp9_idct_idct_16x16_add_10 %+ SUFFIX).idctfull
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; dc-only
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jmp mangle(private_prefix %+ _ %+ vp9_idct_idct_16x16_add_10 %+ SUFFIX).idctfull
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; dc-only - unfortunately, this one can overflow, since coefs are 19+sign
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; bpp, and 19+14+sign does not fit in 32bit, so we do 2-stage multiplies
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DEFINE_ARGS dst, stride, block, coef, coefl
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pxor m2, m2
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DC_ONLY_64BIT 6, m2
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movd m1, coefd
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pshuflw m1, m1, q0000
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punpcklqdq m1, m1
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DEFINE_ARGS dst, stride, cnt
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mov cntd, 8
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.loop_dc:
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STORE_2x8 3, 4, 1, m2, m0, dstq, mmsize
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STORE_2x8 3, 4, 1, m2, m0, dstq+strideq, mmsize
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lea dstq, [dstq+strideq*2]
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dec cntd
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jg .loop_dc
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RET
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