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lavc/aacpsdsp: fix clobber on RISC-V LP64D/ILP32D

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Although the DSP function only uses single precision from RISC-V F, the
caller may leave double precision values in the spilled registers if the
calling convention supports double precision hardware floats. Then, we
need to save and restore FS registers as double precision.

Conversely, we do not need to save anything at all if an integer calling
convention is in use. However we can assume that single precision floats
are supported, since the Zve32f extension implies the F extension.
So for the sake of simplicity, we always save at least single precision
values.

In theory, we should even save quadruple precision values if the LP64Q
ABI is in use. I have yet to see a compiler that supports it though.
This commit is contained in:
Rémi Denis-Courmont 2022-10-06 21:46:12 +03:00 committed by Lynne
parent bfc69297c5
commit 105921251a
1 changed files with 6 additions and 4 deletions
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10
libavcodec/riscv/aacpsdsp_rvv.S
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@ -55,9 +55,10 @@ endfunc
func ff_ps_hybrid_analysis_rvv, zve32f func ff_ps_hybrid_analysis_rvv, zve32f
/* We need 26 FP registers, for 20 scratch ones. Spill fs0-fs5. */ /* We need 26 FP registers, for 20 scratch ones. Spill fs0-fs5. */
addi sp, sp, -32 addi sp, sp, -48
.irp n, 0, 1, 2, 3, 4, 5 .irp n, 0, 1, 2, 3, 4, 5
fsw fs\n, (4 * \n)(sp) HWD fsd fs\n, (8 * \n)(sp)
NOHWD fsw fs\n, (4 * \n)(sp)
.endr .endr
.macro input, j, fd0, fd1, fd2, fd3 .macro input, j, fd0, fd1, fd2, fd3
@ -142,9 +143,10 @@ func ff_ps_hybrid_analysis_rvv, zve32f
bnez a4, 1b bnez a4, 1b
.irp n, 5, 4, 3, 2, 1, 0 .irp n, 5, 4, 3, 2, 1, 0
flw fs\n, (4 * \n)(sp) HWD fld fs\n, (8 * \n)(sp)
NOHWD flw fs\n, (4 * \n)(sp)
.endr .endr
addi sp, sp, 32 addi sp, sp, 48
ret ret
.purgem input .purgem input
.purgem filter .purgem filter