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avutil/mips: Avoid instruction exception caused by gssqc1/gslqc1.
Ensure the address accesed by gssqc1/gslqc1 are 16-byte aligned.
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@ -39,7 +39,7 @@
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#define COL_SHIFT 20
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#define DC_SHIFT 3
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DECLARE_ALIGNED(8, const int16_t, W_arr)[46] = {
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DECLARE_ALIGNED(16, const int16_t, W_arr)[46] = {
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W4, W2, W4, W6,
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W1, W3, W5, W7,
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W4, W6, -W4, -W2,
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@ -205,7 +205,7 @@
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* backup register
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*/
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#define BACKUP_REG \
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double temp_backup_reg[8]; \
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LOCAL_ALIGNED_16(double, temp_backup_reg, [8]); \
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if (_MIPS_SIM == _ABI64) \
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__asm__ volatile ( \
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"gssqc1 $f25, $f24, 0x00(%[temp]) \n\t" \
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