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avcodec/x86/videodsp: Properly mark sse2 instructions in emulated_edge_mc x86 simd as such.
Should fix crashes or corrupt output on pre-SSE2 CPUs when they were using SSE2-code (e.g. AMD Athlon XP 2400+ or Intel Pentium III) in hfix or hvar single-edge (left/right) extension functions. Tested-by: Ingo Brückl <ib@wupperonline.de> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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@ -100,10 +100,10 @@ cglobal emu_edge_hvar, 5, 6, 1, dst, dst_stride, start_x, n_words, h, w
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; FIXME also write a ssse3 version using pshufb
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movzx wd, byte [dstq+start_xq] ; w = read(1)
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imul wd, 0x01010101 ; w *= 0x01010101
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movd m0, wd ; FIXME this is sse2, not sse
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movd m0, wd
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mov wq, n_wordsq ; initialize w
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%if cpuflag(sse)
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shufps m0, m0, q0000 ; splat
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%if cpuflag(sse2)
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pshufd m0, m0, q0000 ; splat
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%else ; mmx
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punpckldq m0, m0 ; splat
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%endif ; mmx/sse
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@ -124,7 +124,7 @@ INIT_MMX mmx
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hvar_fn
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%endif
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INIT_XMM sse
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INIT_XMM sse2
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hvar_fn
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; macro to read/write a horizontal number of pixels (%2) to/from registers
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@ -353,7 +353,7 @@ VERTICAL_EXTEND 16, 22
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%if %1 >= 8
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movd m0, vald
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%if mmsize == 16
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shufps m0, m0, q0000
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pshufd m0, m0, q0000
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%else
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punpckldq m0, m0
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%endif
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@ -423,7 +423,7 @@ H_EXTEND 2, 14
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H_EXTEND 16, 22
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%endif
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INIT_XMM sse
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INIT_XMM sse2
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H_EXTEND 16, 22
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%macro PREFETCH_FN 1
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@ -117,17 +117,17 @@ static emu_edge_hfix_func *hfixtbl_mmx[11] = {
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};
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#endif
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extern emu_edge_hvar_func ff_emu_edge_hvar_mmx;
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extern emu_edge_hfix_func ff_emu_edge_hfix16_sse;
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extern emu_edge_hfix_func ff_emu_edge_hfix18_sse;
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extern emu_edge_hfix_func ff_emu_edge_hfix20_sse;
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extern emu_edge_hfix_func ff_emu_edge_hfix22_sse;
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static emu_edge_hfix_func *hfixtbl_sse[11] = {
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extern emu_edge_hfix_func ff_emu_edge_hfix16_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix18_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix20_sse2;
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extern emu_edge_hfix_func ff_emu_edge_hfix22_sse2;
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static emu_edge_hfix_func *hfixtbl_sse2[11] = {
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ff_emu_edge_hfix2_mmx, ff_emu_edge_hfix4_mmx, ff_emu_edge_hfix6_mmx,
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ff_emu_edge_hfix8_mmx, ff_emu_edge_hfix10_mmx, ff_emu_edge_hfix12_mmx,
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ff_emu_edge_hfix14_mmx, ff_emu_edge_hfix16_sse, ff_emu_edge_hfix18_sse,
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ff_emu_edge_hfix20_sse, ff_emu_edge_hfix22_sse
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ff_emu_edge_hfix14_mmx, ff_emu_edge_hfix16_sse2, ff_emu_edge_hfix18_sse2,
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ff_emu_edge_hfix20_sse2, ff_emu_edge_hfix22_sse2
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};
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extern emu_edge_hvar_func ff_emu_edge_hvar_sse;
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extern emu_edge_hvar_func ff_emu_edge_hvar_sse2;
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static av_always_inline void emulated_edge_mc(uint8_t *dst, ptrdiff_t dst_stride,
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const uint8_t *src, ptrdiff_t src_stride,
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@ -212,21 +212,26 @@ static av_noinline void emulated_edge_mc_mmx(uint8_t *buf, ptrdiff_t buf_stride,
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src_x, src_y, w, h, vfixtbl_mmx, &ff_emu_edge_vvar_mmx,
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hfixtbl_mmx, &ff_emu_edge_hvar_mmx);
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}
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#endif
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static av_noinline void emulated_edge_mc_sse(uint8_t *buf, ptrdiff_t buf_stride,
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const uint8_t *src, ptrdiff_t src_stride,
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int block_w, int block_h,
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int src_x, int src_y, int w, int h)
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{
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emulated_edge_mc(buf, buf_stride, src, src_stride, block_w, block_h, src_x,
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src_y, w, h, vfixtbl_sse, &ff_emu_edge_vvar_sse, hfixtbl_sse,
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#if ARCH_X86_64
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&ff_emu_edge_hvar_sse
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#else
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&ff_emu_edge_hvar_mmx
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emulated_edge_mc(buf, buf_stride, src, src_stride, block_w, block_h,
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src_x, src_y, w, h, vfixtbl_sse, &ff_emu_edge_vvar_sse,
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hfixtbl_mmx, &ff_emu_edge_hvar_mmx);
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}
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#endif
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);
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static av_noinline void emulated_edge_mc_sse2(uint8_t *buf, ptrdiff_t buf_stride,
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const uint8_t *src, ptrdiff_t src_stride,
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int block_w, int block_h,
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int src_x, int src_y, int w, int h)
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{
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emulated_edge_mc(buf, buf_stride, src, src_stride, block_w, block_h, src_x,
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src_y, w, h, vfixtbl_sse, &ff_emu_edge_vvar_sse,
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hfixtbl_sse2, &ff_emu_edge_hvar_sse2);
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}
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#endif /* HAVE_YASM */
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@ -249,8 +254,13 @@ av_cold void ff_videodsp_init_x86(VideoDSPContext *ctx, int bpc)
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if (EXTERNAL_MMXEXT(cpu_flags)) {
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ctx->prefetch = ff_prefetch_mmxext;
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}
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#if ARCH_X86_32
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if (EXTERNAL_SSE(cpu_flags) && bpc <= 8) {
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ctx->emulated_edge_mc = emulated_edge_mc_sse;
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}
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#endif /* ARCH_X86_32 */
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if (EXTERNAL_SSE2(cpu_flags) && bpc <= 8) {
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ctx->emulated_edge_mc = emulated_edge_mc_sse2;
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}
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#endif /* HAVE_YASM */
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}
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