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vp9: initial attempt at a idct_idct_4x4 12bpp x86 simd (sse2) impl.
The trouble with this function is that intermediates overflow 31+sign bits, so I've added some helpers (that will also be used in 10/12bpp 8x8, 16x16 and 32x32) to make that easier, basically emulating a half- assed pmaddqd using 2xpmaddwd. It's currently sse2-only, if anyone sees potential in adding ssse3, I'd love to hear it.
This commit is contained in:
Ronald S. Bultje
parent
f76423d097
commit
235e76aeb8
@ -131,6 +131,8 @@ decl_itxfm_func(idct, iadst, 4, BPC, sse2);
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decl_itxfm_func(iadst, idct, 4, BPC, sse2);
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decl_itxfm_func(iadst, iadst, 4, BPC, sse2);
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decl_itxfm_funcs(4, BPC, ssse3);
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#else
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decl_itxfm_func(idct, idct, 4, BPC, sse2);
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#endif
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#endif /* HAVE_YASM */
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@ -199,6 +201,8 @@ av_cold void INIT_FUNC(VP9DSPContext *dsp, int bitexact)
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init_itx_func(TX_4X4, DCT_ADST, iadst, idct, 4, 10, sse2);
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init_itx_func(TX_4X4, ADST_ADST, iadst, iadst, 4, 10, sse2);
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}
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#else
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init_itx_func(TX_4X4, DCT_DCT, idct, idct, 4, 12, sse2);
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#endif
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}
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@ -31,6 +31,9 @@ cextern pw_2048
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cextern pw_4095
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cextern pd_8192
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pd_8: times 4 dd 8
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pd_3fff: times 4 dd 0x3fff
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; FIXME these should probably be shared between 8bpp and 10/12bpp
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pw_m11585_11585: times 4 dw -11585, 11585
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pw_11585_11585: times 8 dw 11585
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@ -268,3 +271,122 @@ INIT_MMX ssse3
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IADST4_FN idct, IDCT4, iadst, IADST4
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IADST4_FN iadst, IADST4, idct, IDCT4
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IADST4_FN iadst, IADST4, iadst, IADST4
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; inputs and outputs are dwords, coefficients are words
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;
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; dst1 = src1 * coef1 + src2 * coef2 + rnd >> 14
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; dst2 = src1 * coef2 - src2 * coef1 + rnd >> 14
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%macro SUMSUB_MUL 6 ; src/dst 1-2, tmp1-2, coef1-2
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pand m%3, m%1, [pd_3fff]
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pand m%4, m%2, [pd_3fff]
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psrad m%1, 14
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psrad m%2, 14
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packssdw m%4, m%2
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packssdw m%3, m%1
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punpckhwd m%2, m%4, m%3
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punpcklwd m%4, m%3
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pmaddwd m%3, m%4, [pw_%6_%5]
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pmaddwd m%1, m%2, [pw_%6_%5]
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pmaddwd m%4, [pw_m%5_%6]
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pmaddwd m%2, [pw_m%5_%6]
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paddd m%3, [pd_8192]
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paddd m%4, [pd_8192]
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psrad m%3, 14
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psrad m%4, 14
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paddd m%1, m%3
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paddd m%2, m%4
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%endmacro
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%macro IDCT4_12BPP_1D 0
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SUMSUB_MUL 0, 2, 4, 5, 11585, 11585
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SUMSUB_MUL 1, 3, 4, 5, 15137, 6270
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SUMSUB_BA d, 1, 0, 4
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SUMSUB_BA d, 3, 2, 4
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SWAP 1, 3, 0
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%endmacro
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INIT_XMM sse2
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cglobal vp9_idct_idct_4x4_add_12, 4, 4, 6, dst, stride, block, eob
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cmp eobd, 1
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jg .idctfull
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; dc-only - this is special, since for 4x4 12bpp, the max coef size is
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; 17+sign bpp. Since the multiply is with 11585, which is 14bpp, the
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; result of each multiply is 31+sign bit, i.e. it _exactly_ fits in a
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; dword. After the final shift (4), the result is 13+sign bits, so we
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; don't need any additional processing to fit it in a word
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DEFINE_ARGS dst, stride, block, coef
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mov coefd, dword [blockq]
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imul coefd, 11585
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add coefd, 8192
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sar coefd, 14
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imul coefd, 11585
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add coefd, (8 << 14) + 8192
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sar coefd, 14 + 4
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movd m0, coefd
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pshuflw m0, m0, q0000
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punpcklqdq m0, m0
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pxor m4, m4
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mova m5, [pw_4095]
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movd [blockq], m4
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DEFINE_ARGS dst, stride, stride3
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lea stride3q, [strideq*3]
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movh m1, [dstq+strideq*0]
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movh m3, [dstq+strideq*2]
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movhps m1, [dstq+strideq*1]
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movhps m3, [dstq+stride3q ]
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paddw m1, m0
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paddw m3, m0
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pmaxsw m1, m4
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pmaxsw m3, m4
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pminsw m1, m5
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pminsw m3, m5
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movh [dstq+strideq*0], m1
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movhps [dstq+strideq*1], m1
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movh [dstq+strideq*2], m3
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movhps [dstq+stride3q ], m3
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RET
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.idctfull:
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DEFINE_ARGS dst, stride, block, eob
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mova m0, [blockq+0*16]
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mova m1, [blockq+1*16]
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mova m2, [blockq+2*16]
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mova m3, [blockq+3*16]
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IDCT4_12BPP_1D
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TRANSPOSE4x4D 0, 1, 2, 3, 4
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IDCT4_12BPP_1D
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pxor m4, m4
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ZERO_BLOCK blockq, 16, 4, m4
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; writeout
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DEFINE_ARGS dst, stride, stride3
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lea stride3q, [strideq*3]
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paddd m0, [pd_8]
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paddd m1, [pd_8]
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paddd m2, [pd_8]
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paddd m3, [pd_8]
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psrad m0, 4
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psrad m1, 4
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psrad m2, 4
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psrad m3, 4
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packssdw m0, m1
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packssdw m2, m3
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mova m5, [pw_4095]
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movh m1, [dstq+strideq*0]
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movh m3, [dstq+strideq*2]
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movhps m1, [dstq+strideq*1]
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movhps m3, [dstq+stride3q ]
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paddw m0, m1
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paddw m2, m3
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pmaxsw m0, m4
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pmaxsw m2, m4
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pminsw m0, m5
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pminsw m2, m5
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movh [dstq+strideq*0], m0
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movhps [dstq+strideq*1], m0
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movh [dstq+strideq*2], m2
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movhps [dstq+stride3q ], m2
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RET
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