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arm: Add VFP-accelerated version of synth_filter_float
Before After Mean StdDev Mean StdDev Change This function 9295.0 114.9 4853.2 83.5 +91.5% Overall 23699.8 397.6 19285.5 292.0 +22.9% Signed-off-by: Martin Storsjö <martin@martin.st>
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@ -52,6 +52,7 @@ ARMV6-OBJS-$(CONFIG_VP8_DECODER) += arm/vp8_armv6.o \
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arm/vp8dsp_init_armv6.o \
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arm/vp8dsp_armv6.o
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VFP-OBJS-$(CONFIG_DCA_DECODER) += arm/synth_filter_vfp.o
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VFP-OBJS-$(HAVE_ARMV6) += arm/fmtconvert_vfp.o
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NEON-OBJS += arm/fmtconvert_neon.o
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@ -32,6 +32,12 @@ void ff_mdct_calc_neon(FFTContext *s, FFTSample *output, const FFTSample *input)
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void ff_rdft_calc_neon(struct RDFTContext *s, FFTSample *z);
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void ff_synth_filter_float_vfp(FFTContext *imdct,
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float *synth_buf_ptr, int *synth_buf_offset,
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float synth_buf2[32], const float window[512],
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float out[32], const float in[32],
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float scale);
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void ff_synth_filter_float_neon(FFTContext *imdct,
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float *synth_buf_ptr, int *synth_buf_offset,
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float synth_buf2[32], const float window[512],
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@ -69,6 +75,8 @@ av_cold void ff_synth_filter_init_arm(SynthFilterContext *s)
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{
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int cpu_flags = av_get_cpu_flags();
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if (have_vfp(cpu_flags) && !have_vfpv3(cpu_flags))
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s->synth_filter_float = ff_synth_filter_float_vfp;
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if (have_neon(cpu_flags))
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s->synth_filter_float = ff_synth_filter_float_neon;
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}
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243
libavcodec/arm/synth_filter_vfp.S
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243
libavcodec/arm/synth_filter_vfp.S
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@ -0,0 +1,243 @@
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/*
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* Copyright (c) 2013 RISC OS Open Ltd
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* Author: Ben Avison <bavison@riscosopen.org>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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IMDCT .req r0
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ORIG_P_SB .req r1
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P_SB_OFF .req r2
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I .req r0
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P_SB2_UP .req r1
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OLDFPSCR .req r2
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P_SB2_DN .req r3
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P_WIN_DN .req r4
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P_OUT_DN .req r5
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P_SB .req r6
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J_WRAP .req r7
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P_WIN_UP .req r12
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P_OUT_UP .req r14
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SCALE .req s0
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SBUF_DAT_REV0 .req s4
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SBUF_DAT_REV1 .req s5
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SBUF_DAT_REV2 .req s6
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SBUF_DAT_REV3 .req s7
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VA0 .req s8
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VA3 .req s11
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VB0 .req s12
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VB3 .req s15
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VC0 .req s8
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VC3 .req s11
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VD0 .req s12
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VD3 .req s15
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SBUF_DAT0 .req s16
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SBUF_DAT1 .req s17
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SBUF_DAT2 .req s18
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SBUF_DAT3 .req s19
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SBUF_DAT_ALT0 .req s20
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SBUF_DAT_ALT1 .req s21
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SBUF_DAT_ALT2 .req s22
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SBUF_DAT_ALT3 .req s23
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WIN_DN_DAT0 .req s24
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WIN_UP_DAT0 .req s28
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.macro inner_loop half, tail, head
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.if (OFFSET & (64*4)) == 0 @ even numbered call
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SBUF_DAT_THIS0 .req SBUF_DAT0
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SBUF_DAT_THIS1 .req SBUF_DAT1
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SBUF_DAT_THIS2 .req SBUF_DAT2
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SBUF_DAT_THIS3 .req SBUF_DAT3
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.ifnc "\head",""
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vldr d8, [P_SB, #OFFSET] @ d8 = SBUF_DAT
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vldr d9, [P_SB, #OFFSET+8]
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.endif
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.else
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SBUF_DAT_THIS0 .req SBUF_DAT_ALT0
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SBUF_DAT_THIS1 .req SBUF_DAT_ALT1
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SBUF_DAT_THIS2 .req SBUF_DAT_ALT2
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SBUF_DAT_THIS3 .req SBUF_DAT_ALT3
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.ifnc "\head",""
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vldr d10, [P_SB, #OFFSET] @ d10 = SBUF_DAT_ALT
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vldr d11, [P_SB, #OFFSET+8]
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.endif
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.endif
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.ifnc "\tail",""
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.ifc "\half","ab"
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vmls.f VA0, SBUF_DAT_REV0, WIN_DN_DAT0 @ all operands treated as vectors
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.else
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vmla.f VD0, SBUF_DAT_REV0, WIN_DN_DAT0 @ all operands treated as vectors
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.endif
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.endif
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.ifnc "\head",""
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vldr d14, [P_WIN_UP, #OFFSET] @ d14 = WIN_UP_DAT
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vldr d15, [P_WIN_UP, #OFFSET+8]
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vldr d12, [P_WIN_DN, #OFFSET] @ d12 = WIN_DN_DAT
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vldr d13, [P_WIN_DN, #OFFSET+8]
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vmov SBUF_DAT_REV3, SBUF_DAT_THIS0
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vmov SBUF_DAT_REV2, SBUF_DAT_THIS1
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vmov SBUF_DAT_REV1, SBUF_DAT_THIS2
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vmov SBUF_DAT_REV0, SBUF_DAT_THIS3
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.ifc "\half","ab"
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vmla.f VB0, SBUF_DAT_THIS0, WIN_UP_DAT0
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.else
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vmla.f VC0, SBUF_DAT_THIS0, WIN_UP_DAT0
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.endif
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teq J_WRAP, #J
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bne 2f @ strongly predictable, so better than cond exec in this case
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sub P_SB, P_SB, #512*4
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2:
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.set J, J - 64
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.set OFFSET, OFFSET + 64*4
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.endif
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.unreq SBUF_DAT_THIS0
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.unreq SBUF_DAT_THIS1
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.unreq SBUF_DAT_THIS2
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.unreq SBUF_DAT_THIS3
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.endm
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/* void ff_synth_filter_float_vfp(FFTContext *imdct,
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* float *synth_buf_ptr, int *synth_buf_offset,
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* float synth_buf2[32], const float window[512],
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* float out[32], const float in[32], float scale)
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*/
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function ff_synth_filter_float_vfp, export=1
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push {r3-r7,lr}
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vpush {s16-s31}
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ldr lr, [P_SB_OFF]
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add a2, ORIG_P_SB, lr, LSL #2 @ calculate synth_buf to pass to imdct_half
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mov P_SB, a2 @ and keep a copy for ourselves
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bic J_WRAP, lr, #63 @ mangled to make testing for wrap easier in inner loop
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sub lr, lr, #32
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and lr, lr, #512-32
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str lr, [P_SB_OFF] @ rotate offset, modulo buffer size, ready for next call
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ldr a3, [sp, #(16+6+2)*4] @ fetch in from stack, to pass to imdct_half
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VFP vmov s16, SCALE @ imdct_half is free to corrupt s0, but it contains one of our arguments in hardfp case
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bl ff_imdct_half_c
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VFP vmov SCALE, s16
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fmrx OLDFPSCR, FPSCR
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ldr lr, =0x03030000 @ RunFast mode, short vectors of length 4, stride 1
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fmxr FPSCR, lr
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ldr P_SB2_DN, [sp, #16*4]
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ldr P_WIN_DN, [sp, #(16+6+0)*4]
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ldr P_OUT_DN, [sp, #(16+6+1)*4]
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NOVFP vldr SCALE, [sp, #(16+6+3)*4]
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#define IMM_OFF_SKEW 956 /* also valid immediate constant when you add 16*4 */
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add P_SB, P_SB, #IMM_OFF_SKEW @ so we can use -ve offsets to use full immediate offset range
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add P_SB2_UP, P_SB2_DN, #16*4
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add P_WIN_UP, P_WIN_DN, #16*4+IMM_OFF_SKEW
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add P_OUT_UP, P_OUT_DN, #16*4
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add P_SB2_DN, P_SB2_DN, #16*4
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add P_WIN_DN, P_WIN_DN, #12*4+IMM_OFF_SKEW
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add P_OUT_DN, P_OUT_DN, #16*4
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mov I, #4
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1:
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vldmia P_SB2_UP!, {VB0-VB3}
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vldmdb P_SB2_DN!, {VA0-VA3}
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.set J, 512 - 64
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.set OFFSET, -IMM_OFF_SKEW
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inner_loop ab,, head
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.rept 7
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inner_loop ab, tail, head
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.endr
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inner_loop ab, tail
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add P_WIN_UP, P_WIN_UP, #4*4
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sub P_WIN_DN, P_WIN_DN, #4*4
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vmul.f VB0, VB0, SCALE @ SCALE treated as scalar
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add P_SB, P_SB, #(512+4)*4
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subs I, I, #1
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vmul.f VA0, VA0, SCALE
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vstmia P_OUT_UP!, {VB0-VB3}
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vstmdb P_OUT_DN!, {VA0-VA3}
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bne 1b
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add P_SB2_DN, P_SB2_DN, #(16+28-12)*4
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sub P_SB2_UP, P_SB2_UP, #(16+16)*4
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add P_WIN_DN, P_WIN_DN, #(32+16+28-12)*4
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mov I, #4
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1:
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vldr.d d4, zero @ d4 = VC0
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vldr.d d5, zero
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vldr.d d6, zero @ d6 = VD0
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vldr.d d7, zero
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.set J, 512 - 64
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.set OFFSET, -IMM_OFF_SKEW
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inner_loop cd,, head
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.rept 7
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inner_loop cd, tail, head
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.endr
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inner_loop cd, tail
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add P_WIN_UP, P_WIN_UP, #4*4
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sub P_WIN_DN, P_WIN_DN, #4*4
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add P_SB, P_SB, #(512+4)*4
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subs I, I, #1
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vstmia P_SB2_UP!, {VC0-VC3}
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vstmdb P_SB2_DN!, {VD0-VD3}
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bne 1b
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fmxr FPSCR, OLDFPSCR
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vpop {s16-s31}
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pop {r3-r7,pc}
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endfunc
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.unreq IMDCT
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.unreq ORIG_P_SB
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.unreq P_SB_OFF
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.unreq I
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.unreq P_SB2_UP
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.unreq OLDFPSCR
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.unreq P_SB2_DN
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.unreq P_WIN_DN
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.unreq P_OUT_DN
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.unreq P_SB
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.unreq J_WRAP
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.unreq P_WIN_UP
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.unreq P_OUT_UP
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.unreq SCALE
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.unreq SBUF_DAT_REV0
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.unreq SBUF_DAT_REV1
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.unreq SBUF_DAT_REV2
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.unreq SBUF_DAT_REV3
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.unreq VA0
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.unreq VA3
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.unreq VB0
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.unreq VB3
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.unreq VC0
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.unreq VC3
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.unreq VD0
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.unreq VD3
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.unreq SBUF_DAT0
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.unreq SBUF_DAT1
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.unreq SBUF_DAT2
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.unreq SBUF_DAT3
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.unreq SBUF_DAT_ALT0
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.unreq SBUF_DAT_ALT1
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.unreq SBUF_DAT_ALT2
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.unreq SBUF_DAT_ALT3
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.unreq WIN_DN_DAT0
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.unreq WIN_UP_DAT0
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.align 3
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zero: .word 0, 0
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