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lavu/floatdsp: RISC-V V vector_fmul

This commit is contained in:
Rémi Denis-Courmont 2022-09-26 17:52:30 +03:00 committed by Lynne
parent 89b7ec65a8
commit 7058af9969
2 changed files with 22 additions and 1 deletions

View File

@ -25,6 +25,8 @@
#include "libavutil/cpu.h"
#include "libavutil/float_dsp.h"
void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
int len);
void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
int len);
@ -36,8 +38,10 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
#if HAVE_RVV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVV_F32)
if (flags & AV_CPU_FLAG_RVV_F32) {
fdsp->vector_fmul = ff_vector_fmul_rvv;
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
}
if (flags & AV_CPU_FLAG_RVV_F64)
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;

View File

@ -21,6 +21,23 @@
#include "config.h"
#include "asm.S"
// (a0) = (a1) * (a2) [0..a3-1]
func ff_vector_fmul_rvv, zve32f
1:
vsetvli t0, a3, e32, m1, ta, ma
vle32.v v16, (a1)
sub a3, a3, t0
vle32.v v24, (a2)
sh2add a1, t0, a1
vfmul.vv v16, v16, v24
sh2add a2, t0, a2
vse32.v v16, (a0)
sh2add a0, t0, a0
bnez a3, 1b
ret
endfunc
// (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_fmul_scalar_rvv, zve32f
NOHWF fmv.w.x fa0, a2