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avutil/mips: Use $at as MMI macro temporary register
Some function had exceed 30 inline assembly register oprands limiation when using LOONGSON2 version of MMI macros. We can avoid that by take $at, which is register reserved for assembler, as temporary register. As none of instructions used in these macros is pseudo, it is safe to utilize $at here. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Shiyou Yin <yinshiyou-hf@loongson.cn> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
This commit is contained in:
Jiaxun Yang
Michael Niedermayer
parent
1042039ccd
commit
a1cd62883f
@ -29,74 +29,103 @@
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#include "libavutil/mem_internal.h"
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#include "libavutil/mips/asmdefs.h"
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/*
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* These were used to define temporary registers for MMI marcos
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* however now we're using $at. They're theoretically unnecessary
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* but just leave them here to avoid mess.
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*/
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#define DECLARE_VAR_LOW32
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#define RESTRICT_ASM_LOW32
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#define DECLARE_VAR_ALL64
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#define RESTRICT_ASM_ALL64
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#define DECLARE_VAR_ADDRT
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#define RESTRICT_ASM_ADDRT
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#if HAVE_LOONGSON2
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#define DECLARE_VAR_LOW32 int32_t low32
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#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32),
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#define DECLARE_VAR_ALL64 int64_t all64
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#define RESTRICT_ASM_ALL64 [all64]"=&r"(all64),
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#define DECLARE_VAR_ADDRT mips_reg addrt
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#define RESTRICT_ASM_ADDRT [addrt]"=&r"(addrt),
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#define MMI_LWX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"lw "#reg", "#bias"(%[addrt]) \n\t"
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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"lw "#reg", "#bias"($at) \n\t" \
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".set at \n\t"
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#define MMI_SWX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"sw "#reg", "#bias"(%[addrt]) \n\t"
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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"sw "#reg", "#bias"($at) \n\t" \
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".set at \n\t"
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#define MMI_LDX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"ld "#reg", "#bias"(%[addrt]) \n\t"
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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"ld "#reg", "#bias"($at) \n\t" \
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".set at \n\t"
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#define MMI_SDX(reg, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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"sd "#reg", "#bias"(%[addrt]) \n\t"
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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"sd "#reg", "#bias"($at) \n\t" \
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".set at \n\t"
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#define MMI_LWC1(fp, addr, bias) \
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"lwc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_ULWC1(fp, addr, bias) \
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"ulw %[low32], "#bias"("#addr") \n\t" \
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"mtc1 %[low32], "#fp" \n\t"
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".set noat \n\t" \
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"ulw $at, "#bias"("#addr") \n\t" \
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"mtc1 $at, "#fp" \n\t" \
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".set at \n\t"
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#define MMI_LWXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_LWC1(fp, %[addrt], bias)
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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MMI_LWC1(fp, $at, bias) \
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".set at \n\t"
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#define MMI_SWC1(fp, addr, bias) \
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"swc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_USWC1(fp, addr, bias) \
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"mfc1 %[low32], "#fp" \n\t" \
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"usw %[low32], "#bias"("#addr") \n\t"
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".set noat \n\t" \
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"mfc1 $at, "#fp" \n\t" \
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"usw $at, "#bias"("#addr") \n\t" \
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".set at \n\t"
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#define MMI_SWXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_SWC1(fp, %[addrt], bias)
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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MMI_SWC1(fp, $at, bias) \
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".set at \n\t"
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#define MMI_LDC1(fp, addr, bias) \
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"ldc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_ULDC1(fp, addr, bias) \
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"uld %[all64], "#bias"("#addr") \n\t" \
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"dmtc1 %[all64], "#fp" \n\t"
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".set noat \n\t" \
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"uld $at, "#bias"("#addr") \n\t" \
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"dmtc1 $at, "#fp" \n\t" \
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".set at \n\t"
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#define MMI_LDXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_LDC1(fp, %[addrt], bias)
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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MMI_LDC1(fp, $at, bias) \
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".set at \n\t"
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#define MMI_SDC1(fp, addr, bias) \
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"sdc1 "#fp", "#bias"("#addr") \n\t"
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#define MMI_USDC1(fp, addr, bias) \
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"dmfc1 %[all64], "#fp" \n\t" \
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"usd %[all64], "#bias"("#addr") \n\t"
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".set noat \n\t" \
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"dmfc1 $at, "#fp" \n\t" \
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"usd $at, "#bias"("#addr") \n\t" \
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".set at \n\t"
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#define MMI_SDXC1(fp, addr, stride, bias) \
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PTR_ADDU "%[addrt], "#addr", "#stride" \n\t" \
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MMI_SDC1(fp, %[addrt], bias)
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".set noat \n\t" \
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PTR_ADDU "$at, "#addr", "#stride" \n\t" \
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MMI_SDC1(fp, $at, bias) \
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".set at \n\t"
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#define MMI_LQ(reg1, reg2, addr, bias) \
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"ld "#reg1", "#bias"("#addr") \n\t" \
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@ -116,11 +145,6 @@
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#elif HAVE_LOONGSON3 /* !HAVE_LOONGSON2 */
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#define DECLARE_VAR_ALL64
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#define RESTRICT_ASM_ALL64
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#define DECLARE_VAR_ADDRT
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#define RESTRICT_ASM_ADDRT
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#define MMI_LWX(reg, addr, stride, bias) \
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"gslwx "#reg", "#bias"("#addr", "#stride") \n\t"
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@ -138,12 +162,12 @@
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#if _MIPS_SIM == _ABIO32 /* workaround for 3A2000 gslwlc1 bug */
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#define DECLARE_VAR_LOW32 int32_t low32
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#define RESTRICT_ASM_LOW32 [low32]"=&r"(low32),
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#define MMI_ULWC1(fp, addr, bias) \
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"ulw %[low32], "#bias"("#addr") \n\t" \
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"mtc1 %[low32], "#fp" \n\t"
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#define MMI_LWLRC1(fp, addr, bias, off) \
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".set noat \n\t" \
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"lwl $at, "#bias"+"#off"("#addr") \n\t" \
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"lwr $at, "#bias"("#addr") \n\t" \
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"mtc1 $at, "#fp" \n\t" \
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".set at \n\t"
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#else /* _MIPS_SIM != _ABIO32 */
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