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VC1: restore optimizations broken in 9a1ced32
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They were moved into code under HAVE_YASM and most of them even into completely disabled code with no reason given for that in the commit message. Signed-off-by: Reimar Döffinger <Reimar.Doeffinger@gmx.de>
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@ -751,6 +751,8 @@ void ff_vc1dsp_init_mmx(VC1DSPContext *dsp)
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dsp->put_vc1_mspel_pixels_tab[ 7] = put_vc1_mspel_mc31_mmx;
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dsp->put_vc1_mspel_pixels_tab[11] = put_vc1_mspel_mc32_mmx;
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dsp->put_vc1_mspel_pixels_tab[15] = put_vc1_mspel_mc33_mmx;
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dsp->put_no_rnd_vc1_chroma_pixels_tab[0]= ff_put_vc1_chroma_mc8_mmx_nornd;
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}
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if (mm_flags & AV_CPU_FLAG_MMX2){
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@ -778,6 +780,15 @@ void ff_vc1dsp_init_mmx(VC1DSPContext *dsp)
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dsp->vc1_inv_trans_4x8_dc = vc1_inv_trans_4x8_dc_mmx2;
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dsp->vc1_inv_trans_8x4_dc = vc1_inv_trans_8x4_dc_mmx2;
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dsp->vc1_inv_trans_4x4_dc = vc1_inv_trans_4x4_dc_mmx2;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0]= ff_avg_vc1_chroma_mc8_mmx2_nornd;
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} else if (mm_flags & AV_CPU_FLAG_3DNOW) {
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0]= ff_avg_vc1_chroma_mc8_3dnow_nornd;
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}
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if (mm_flags & AV_CPU_FLAG_SSSE3) {
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dsp->put_no_rnd_vc1_chroma_pixels_tab[0]= ff_put_vc1_chroma_mc8_ssse3_nornd;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0]= ff_avg_vc1_chroma_mc8_ssse3_nornd;
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}
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#define ASSIGN_LF(EXT) \
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@ -791,14 +802,10 @@ void ff_vc1dsp_init_mmx(VC1DSPContext *dsp)
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#if HAVE_YASM
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if (mm_flags & AV_CPU_FLAG_MMX) {
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ASSIGN_LF(mmx);
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dsp->put_no_rnd_vc1_chroma_pixels_tab[0]= ff_put_vc1_chroma_mc8_mmx_nornd;
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}
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return;
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if (mm_flags & AV_CPU_FLAG_MMX2) {
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ASSIGN_LF(mmx2);
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0]= ff_avg_vc1_chroma_mc8_mmx2_nornd;
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} else if (mm_flags & AV_CPU_FLAG_3DNOW) {
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0]= ff_avg_vc1_chroma_mc8_3dnow_nornd;
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}
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if (mm_flags & AV_CPU_FLAG_SSE2) {
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@ -809,8 +816,6 @@ void ff_vc1dsp_init_mmx(VC1DSPContext *dsp)
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}
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if (mm_flags & AV_CPU_FLAG_SSSE3) {
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ASSIGN_LF(ssse3);
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dsp->put_no_rnd_vc1_chroma_pixels_tab[0]= ff_put_vc1_chroma_mc8_ssse3_nornd;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0]= ff_avg_vc1_chroma_mc8_ssse3_nornd;
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}
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if (mm_flags & AV_CPU_FLAG_SSE4) {
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dsp->vc1_h_loop_filter8 = ff_vc1_h_loop_filter8_sse4;
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