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lavc/aarch64: Add neon implementation of vsse16
Provide optimized implementation of vsse16 for arm64. Performance comparison tests are shown below. - vsse_0_c: 257.7 - vsse_0_neon: 59.2 Benchmarks and tests are run with checkasm tool on AWS Graviton 3. Signed-off-by: Hubert Mazur <hum@semihalf.com> Signed-off-by: Martin Storsjö <martin@martin.st>
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@ -43,6 +43,8 @@ int sse4_neon(MpegEncContext *v, const uint8_t *pix1, const uint8_t *pix2,
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int vsad16_neon(MpegEncContext *c, const uint8_t *s1, const uint8_t *s2,
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ptrdiff_t stride, int h);
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int vsse16_neon(MpegEncContext *c, const uint8_t *s1, const uint8_t *s2,
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ptrdiff_t stride, int h);
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av_cold void ff_me_cmp_init_aarch64(MECmpContext *c, AVCodecContext *avctx)
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{
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@ -62,5 +64,7 @@ av_cold void ff_me_cmp_init_aarch64(MECmpContext *c, AVCodecContext *avctx)
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c->sse[2] = sse4_neon;
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c->vsad[0] = vsad16_neon;
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c->vsse[0] = vsse16_neon;
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}
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}
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@ -649,3 +649,90 @@ function vsad16_neon, export=1
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ret
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endfunc
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function vsse16_neon, export=1
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// x0 unused
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// x1 uint8_t *pix1
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// x2 uint8_t *pix2
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// x3 ptrdiff_t stride
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// w4 int h
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ld1 {v0.16b}, [x1], x3 // Load pix1[0], first iteration
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ld1 {v1.16b}, [x2], x3 // Load pix2[0], first iteration
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sub w4, w4, #1 // we need to make h-1 iterations
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movi v16.4s, #0
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movi v17.4s, #0
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cmp w4, #3 // check if we can make 3 iterations at once
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usubl v31.8h, v0.8b, v1.8b // Signed difference of pix1[0] - pix2[0], first iteration
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usubl2 v30.8h, v0.16b, v1.16b // Signed difference of pix1[0] - pix2[0], first iteration
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b.le 2f
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1:
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// x = abs(pix1[0] - pix2[0] - pix1[0 + stride] + pix2[0 + stride])
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// res = (x) * (x)
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ld1 {v0.16b}, [x1], x3 // Load pix1[0 + stride], first iteration
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ld1 {v1.16b}, [x2], x3 // Load pix2[0 + stride], first iteration
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ld1 {v2.16b}, [x1], x3 // Load pix1[0 + stride], second iteration
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ld1 {v3.16b}, [x2], x3 // Load pix2[0 + stride], second iteration
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usubl v29.8h, v0.8b, v1.8b
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usubl2 v28.8h, v0.16b, v1.16b
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ld1 {v4.16b}, [x1], x3 // Load pix1[0 + stride], third iteration
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ld1 {v5.16b}, [x2], x3 // Load pix1[0 + stride], third iteration
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sabd v31.8h, v31.8h, v29.8h
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sabd v30.8h, v30.8h, v28.8h
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usubl v27.8h, v2.8b, v3.8b
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usubl2 v26.8h, v2.16b, v3.16b
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usubl v25.8h, v4.8b, v5.8b
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usubl2 v24.8h, v4.16b, v5.16b
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sabd v29.8h, v29.8h, v27.8h
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sabd v27.8h, v27.8h, v25.8h
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umlal v16.4s, v31.4h, v31.4h
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umlal2 v17.4s, v31.8h, v31.8h
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sabd v28.8h, v28.8h, v26.8h
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sabd v26.8h, v26.8h, v24.8h
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umlal v16.4s, v30.4h, v30.4h
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umlal2 v17.4s, v30.8h, v30.8h
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mov v31.16b, v25.16b
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umlal v16.4s, v29.4h, v29.4h
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umlal2 v17.4s, v29.8h, v29.8h
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mov v30.16b, v24.16b
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umlal v16.4s, v28.4h, v28.4h
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umlal2 v17.4s, v28.8h, v28.8h
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sub w4, w4, #3
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umlal v16.4s, v27.4h, v27.4h
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umlal2 v17.4s, v27.8h, v27.8h
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cmp w4, #3
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umlal v16.4s, v26.4h, v26.4h
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umlal2 v17.4s, v26.8h, v26.8h
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b.ge 1b
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cbz w4, 3f
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// iterate by once
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2:
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ld1 {v0.16b}, [x1], x3
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ld1 {v1.16b}, [x2], x3
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subs w4, w4, #1
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usubl v29.8h, v0.8b, v1.8b
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usubl2 v28.8h, v0.16b, v1.16b
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sabd v31.8h, v31.8h, v29.8h
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sabd v30.8h, v30.8h, v28.8h
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umlal v16.4s, v31.4h, v31.4h
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umlal2 v17.4s, v31.8h, v31.8h
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mov v31.16b, v29.16b
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umlal v16.4s, v30.4h, v30.4h
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umlal2 v17.4s, v30.8h, v30.8h
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mov v30.16b, v28.16b
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b.ne 2b
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3:
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add v16.4s, v16.4s, v17.4s
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uaddlv d17, v16.4s
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fmov w0, s17
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ret
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endfunc
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