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Revert r24339 (it causes fate failures on x86-64) - I'll figure out what's
wrong with it tomorrow or so, then re-submit. Originally committed as revision 24341 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Ronald S. Bultje
parent
6526976f0c
commit
c60ed66dbe
@ -242,19 +242,6 @@ extern void ff_vp8_h_loop_filter16y_inner_mmxext(uint8_t *dst, int stride,
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int e, int i, int hvt);
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extern void ff_vp8_h_loop_filter16y_inner_sse2 (uint8_t *dst, int stride,
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int e, int i, int hvt);
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extern void ff_vp8_v_loop_filter8uv_inner_mmx (uint8_t *dstU, uint8_t *dstV,
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int s, int e, int i, int hvt);
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extern void ff_vp8_v_loop_filter8uv_inner_mmxext(uint8_t *dstU, uint8_t *dstV,
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int s, int e, int i, int hvt);
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extern void ff_vp8_v_loop_filter8uv_inner_sse2 (uint8_t *dstU, uint8_t *dstV,
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int s, int e, int i, int hvt);
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extern void ff_vp8_h_loop_filter8uv_inner_mmx (uint8_t *dstU, uint8_t *dstV,
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int s, int e, int i, int hvt);
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extern void ff_vp8_h_loop_filter8uv_inner_mmxext(uint8_t *dstU, uint8_t *dstV,
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int s, int e, int i, int hvt);
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extern void ff_vp8_h_loop_filter8uv_inner_sse2 (uint8_t *dstU, uint8_t *dstV,
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int s, int e, int i, int hvt);
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#endif
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#define VP8_LUMA_MC_FUNC(IDX, SIZE, OPT) \
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@ -299,8 +286,6 @@ av_cold void ff_vp8dsp_init_x86(VP8DSPContext* c)
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c->vp8_v_loop_filter16y_inner = ff_vp8_v_loop_filter16y_inner_mmx;
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c->vp8_h_loop_filter16y_inner = ff_vp8_h_loop_filter16y_inner_mmx;
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c->vp8_v_loop_filter8uv_inner = ff_vp8_v_loop_filter8uv_inner_mmx;
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c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_mmx;
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}
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/* note that 4-tap width=16 functions are missing because w=16
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@ -319,8 +304,6 @@ av_cold void ff_vp8dsp_init_x86(VP8DSPContext* c)
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c->vp8_v_loop_filter16y_inner = ff_vp8_v_loop_filter16y_inner_mmxext;
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c->vp8_h_loop_filter16y_inner = ff_vp8_h_loop_filter16y_inner_mmxext;
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c->vp8_v_loop_filter8uv_inner = ff_vp8_v_loop_filter8uv_inner_mmxext;
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c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_mmxext;
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}
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if (mm_flags & FF_MM_SSE) {
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@ -338,12 +321,10 @@ av_cold void ff_vp8dsp_init_x86(VP8DSPContext* c)
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c->vp8_h_loop_filter_simple = ff_vp8_h_loop_filter_simple_sse2;
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c->vp8_v_loop_filter16y_inner = ff_vp8_v_loop_filter16y_inner_sse2;
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c->vp8_v_loop_filter8uv_inner = ff_vp8_v_loop_filter8uv_inner_sse2;
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}
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if (mm_flags & FF_MM_SSE2) {
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c->vp8_h_loop_filter16y_inner = ff_vp8_h_loop_filter16y_inner_sse2;
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c->vp8_h_loop_filter8uv_inner = ff_vp8_h_loop_filter8uv_inner_sse2;
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}
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if (mm_flags & FF_MM_SSSE3) {
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@ -1164,16 +1164,12 @@ cglobal vp8_luma_dc_wht_mmxext, 2,3
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; arguments same as WRITE_2x4D, but with an extra register, so that the 5 regular
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; registers contain buf+4*stride, buf+5*stride, buf+12*stride, -stride and +stride
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; we add 1*stride to the third regular registry in the process
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; the 10th argument is 16 if it's a Y filter (i.e. all regular registers cover the
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; same memory region), or 8 if they cover two separate buffers (third one points to
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; a different memory region than the first two), allowing for more optimal code for
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; the 16-width case
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%macro WRITE_4x4D 10
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%macro WRITE_4x4D 9
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; write out (4 dwords per register), start with dwords zero
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movd [%5+%8*4], m%1
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movd [%5], m%2
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movd [%7+%8*4], m%3
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movd [%7], m%4
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movd [%5+%9*4], m%3
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movd [%5+%9*8], m%4
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; store dwords 1
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psrldq m%1, 4
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@ -1182,23 +1178,15 @@ cglobal vp8_luma_dc_wht_mmxext, 2,3
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psrldq m%4, 4
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movd [%6+%8*4], m%1
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movd [%6], m%2
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%if %10 == 16
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movd [%6+%9*4], m%3
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%endif
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movd [%7+%9], m%4
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movd [%6+%9*8], m%4
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; write dwords 2
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psrldq m%1, 4
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psrldq m%2, 4
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%if %10 == 8
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movd [%5+%8*2], m%1
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movd %5, m%3
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%endif
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psrldq m%3, 4
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psrldq m%4, 4
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%if %10 == 16
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movd [%5+%8*2], m%1
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%endif
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movd [%6+%9], m%2
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movd [%7+%8*2], m%3
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movd [%7+%9*2], m%4
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@ -1209,12 +1197,7 @@ cglobal vp8_luma_dc_wht_mmxext, 2,3
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psrldq m%2, 4
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psrldq m%3, 4
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psrldq m%4, 4
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%if %10 == 8
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mov [%7+%8*4], %5
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movd [%6+%8*2], m%1
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%else
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movd [%5+%8], m%1
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%endif
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movd [%6+%9*2], m%2
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movd [%7+%8*2], m%3
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movd [%7+%9*2], m%4
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@ -1352,7 +1335,7 @@ cglobal vp8_%2_loop_filter_simple_%1, 3, %3
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TRANSPOSE4x4B 0, 1, 2, 3, 4
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%if mmsize == 16 ; sse2
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add r3, r1 ; change from r4*8*stride to r0+8*stride
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WRITE_4x4D 0, 1, 2, 3, r0, r4, r3, r1, r2, 16
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WRITE_4x4D 0, 1, 2, 3, r0, r4, r3, r1, r2
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%else ; mmx/mmxext
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WRITE_4x2D 0, 1, 2, 3, r0, r4, r1, r2
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%endif
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@ -1391,20 +1374,13 @@ SIMPLE_LOOPFILTER sse2, v, 3
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SIMPLE_LOOPFILTER sse2, h, 6
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;-----------------------------------------------------------------------------
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; void vp8_h/v_loop_filter<size>_inner_<opt>(uint8_t *dst, [uint8_t *v,] int stride,
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; void vp8_h/v_loop_filter<size>_inner_<opt>(uint8_t *dst, int stride,
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; int flimE, int flimI, int hev_thr);
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;-----------------------------------------------------------------------------
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%macro INNER_LOOPFILTER 5
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%if %4 == 8 ; chroma
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cglobal vp8_%2_loop_filter8uv_inner_%1, 6, %3, %5
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%define dst8_reg r1
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%define mstride_reg r2
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%define E_reg r3
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%define I_reg r4
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%define hev_thr_reg r5
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%else ; luma
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cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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%macro INNER_LOOPFILTER 4
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cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %4
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%define dst_reg r0
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%define mstride_reg r1
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%define E_reg r2
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%define I_reg r3
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@ -1416,8 +1392,6 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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%else ; x86-32, mmx/mmxext
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%define cnt_reg r5
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%endif
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%endif
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%define dst_reg r0
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%define stride_reg E_reg
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%define dst2_reg I_reg
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%ifndef m8
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@ -1462,16 +1436,13 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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SPLATB_REG hev_thr, hev_thr_reg, %1 ; hev_thresh
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%endif
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%if mmsize == 8 && %4 == 16 ; mmx/mmxext
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%if mmsize == 8 ; mmx/mmxext
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mov cnt_reg, 2
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%endif
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mov stride_reg, mstride_reg
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neg mstride_reg
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%ifidn %2, h
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lea dst_reg, [dst_reg + stride_reg*4-4]
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%if %4 == 8
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lea dst8_reg, [dst8_reg+ stride_reg*4-4]
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%endif
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%endif
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%if mmsize == 8
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@ -1480,27 +1451,12 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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; read
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lea dst2_reg, [dst_reg + stride_reg]
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%ifidn %2, v
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%if %4 == 8 && mmsize == 16
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%define movrow movh
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%else
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%define movrow mova
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%endif
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movrow m0, [dst_reg +mstride_reg*4] ; p3
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movrow m1, [dst2_reg+mstride_reg*4] ; p2
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movrow m2, [dst_reg +mstride_reg*2] ; p1
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movrow m5, [dst2_reg] ; q1
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movrow m6, [dst2_reg+ stride_reg] ; q2
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movrow m7, [dst2_reg+ stride_reg*2] ; q3
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%if mmsize == 16 && %4 == 8
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movhps m0, [dst8_reg+mstride_reg*4]
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movhps m2, [dst8_reg+mstride_reg*2]
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add dst8_reg, stride_reg
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movhps m1, [dst8_reg+mstride_reg*4]
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movhps m5, [dst8_reg]
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movhps m6, [dst8_reg+ stride_reg]
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movhps m7, [dst8_reg+ stride_reg*2]
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add dst8_reg, mstride_reg
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%endif
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mova m0, [dst_reg +mstride_reg*4] ; p3
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mova m1, [dst2_reg+mstride_reg*4] ; p2
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mova m2, [dst_reg +mstride_reg*2] ; p1
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mova m5, [dst2_reg] ; q1
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mova m6, [dst2_reg+ stride_reg] ; q2
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mova m7, [dst2_reg+ stride_reg*2] ; q3
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%elif mmsize == 8 ; mmx/mmxext (h)
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; read 8 rows of 8px each
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movu m0, [dst_reg +mstride_reg*4]
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@ -1541,9 +1497,7 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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SWAP 6, 3
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SWAP 5, 3
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%else ; sse2 (h)
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%if %4 == 16
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lea dst8_reg, [dst_reg + stride_reg*8]
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%endif
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; read 16 rows of 8px each, interleave
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movh m0, [dst_reg +mstride_reg*4]
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@ -1655,10 +1609,7 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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; normal_limit and high_edge_variance for p1-p0, q1-q0
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SWAP 7, 3 ; now m7 is zero
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%ifidn %2, v
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movrow m3, [dst_reg +mstride_reg] ; p0
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%if mmsize == 16 && %4 == 8
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movhps m3, [dst8_reg+mstride_reg]
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%endif
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mova m3, [dst_reg +mstride_reg] ; p0
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%elifdef m14
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SWAP 3, 12
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%else
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@ -1691,10 +1642,7 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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SWAP 6, 4 ; now m6 is I
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%ifidn %2, v
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movrow m4, [dst_reg] ; q0
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%if mmsize == 16 && %4 == 8
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movhps m4, [dst8_reg]
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%endif
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mova m4, [dst_reg] ; q0
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%elifdef m13
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SWAP 4, 8
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%else
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@ -1845,19 +1793,13 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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; store
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%ifidn %2, v
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movrow [dst_reg +mstride_reg*2], m2
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movrow [dst_reg +mstride_reg ], m3
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movrow [dst_reg], m4
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movrow [dst_reg + stride_reg ], m5
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%if mmsize == 16 && %4 == 8
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movhps [dst8_reg+mstride_reg*2], m2
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movhps [dst8_reg+mstride_reg ], m3
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movhps [dst8_reg], m4
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movhps [dst8_reg+ stride_reg ], m5
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%endif
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mova [dst_reg+mstride_reg*2], m2
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mova [dst_reg+mstride_reg ], m3
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mova [dst_reg], m4
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mova [dst_reg+ stride_reg ], m5
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%else ; h
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add dst_reg, 2
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add dst2_reg, 2
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add dst_reg, 2
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add dst2_reg, 2
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; 4x8/16 transpose
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TRANSPOSE4x4B 2, 3, 4, 5, 6
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@ -1866,19 +1808,11 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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WRITE_4x2D 2, 3, 4, 5, dst_reg, dst2_reg, mstride_reg, stride_reg
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%else ; sse2 (h)
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lea dst8_reg, [dst8_reg+mstride_reg+2]
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WRITE_4x4D 2, 3, 4, 5, dst_reg, dst2_reg, dst8_reg, mstride_reg, stride_reg, %4
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WRITE_4x4D 2, 3, 4, 5, dst_reg, dst2_reg, dst8_reg, mstride_reg, stride_reg
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%endif
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%endif
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%if mmsize == 8
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%if %4 == 8 ; chroma
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%ifidn %2, h
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sub dst_reg, 2
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%endif
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cmp dst_reg, dst8_reg
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mov dst_reg, dst8_reg
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jnz .next8px
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%else
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%ifidn %2, h
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lea dst_reg, [dst_reg + stride_reg*8-2]
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%else ; v
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@ -1887,7 +1821,6 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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dec cnt_reg
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jg .next8px
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%endif
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%endif
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%ifndef m8 ; sse2 on x86-32 or mmx/mmxext
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mov rsp, stack_reg ; restore stack pointer
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@ -1896,23 +1829,14 @@ cglobal vp8_%2_loop_filter16y_inner_%1, 5, %3, %5
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%endmacro
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INIT_MMX
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INNER_LOOPFILTER mmx, v, 6, 16, 8
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INNER_LOOPFILTER mmx, h, 6, 16, 8
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INNER_LOOPFILTER mmxext, v, 6, 16, 8
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INNER_LOOPFILTER mmxext, h, 6, 16, 8
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INNER_LOOPFILTER mmx, v, 6, 8, 8
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INNER_LOOPFILTER mmx, h, 6, 8, 8
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INNER_LOOPFILTER mmxext, v, 6, 8, 8
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INNER_LOOPFILTER mmxext, h, 6, 8, 8
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INNER_LOOPFILTER mmx, v, 6, 8
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INNER_LOOPFILTER mmx, h, 6, 8
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INNER_LOOPFILTER mmxext, v, 6, 8
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INNER_LOOPFILTER mmxext, h, 6, 8
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INIT_XMM
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INNER_LOOPFILTER sse2, v, 5, 16, 13
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INNER_LOOPFILTER sse2, v, 5, 13
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%ifdef m8
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INNER_LOOPFILTER sse2, h, 5, 16, 13
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INNER_LOOPFILTER sse2, h, 5, 13
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%else
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INNER_LOOPFILTER sse2, h, 6, 16, 13
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INNER_LOOPFILTER sse2, h, 6, 13
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%endif
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INNER_LOOPFILTER sse2, v, 6, 8, 13
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INNER_LOOPFILTER sse2, h, 6, 8, 13
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