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avcodec/mips: MSA (MIPS-SIMD-Arch) optimizations for HEVC uniw mc functions
This patch adds MSA (MIPS-SIMD-Arch) optimizations for HEVC uniw mc functions (qpel as well as epel) in new file hevc_mc_uniw_msa.c Adds new generic macros (needed for this patch) in libavutil/mips/generic_macros_msa.h Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Shivraj Patil
Michael Niedermayer
parent
d7a762553c
commit
ce1761db19
@ -23,6 +23,7 @@ OBJS-$(CONFIG_H264DSP) += mips/h264dsp_init_mips.o
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OBJS-$(CONFIG_H264CHROMA) += mips/h264chroma_init_mips.o
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MSA-OBJS-$(CONFIG_HEVC_DECODER) += mips/hevcdsp_msa.o \
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mips/hevc_mc_uni_msa.o \
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mips/hevc_mc_uniw_msa.o \
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mips/hevc_mc_bi_msa.o
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MSA-OBJS-$(CONFIG_H264DSP) += mips/h264dsp_msa.o
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LOONGSON3-OBJS-$(CONFIG_H264DSP) += mips/h264dsp_mmi.o
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4790
libavcodec/mips/hevc_mc_uniw_msa.c
Normal file
4790
libavcodec/mips/hevc_mc_uniw_msa.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -97,6 +97,99 @@ static av_cold void hevc_dsp_init_msa(HEVCDSPContext *c,
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c->put_hevc_qpel_uni[8][1][1] = ff_hevc_put_hevc_uni_qpel_hv48_8_msa;
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c->put_hevc_qpel_uni[9][1][1] = ff_hevc_put_hevc_uni_qpel_hv64_8_msa;
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c->put_hevc_qpel_uni_w[1][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels4_8_msa;
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c->put_hevc_qpel_uni_w[3][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels8_8_msa;
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c->put_hevc_qpel_uni_w[4][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels12_8_msa;
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c->put_hevc_qpel_uni_w[5][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels16_8_msa;
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c->put_hevc_qpel_uni_w[6][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels24_8_msa;
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c->put_hevc_qpel_uni_w[7][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels32_8_msa;
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c->put_hevc_qpel_uni_w[8][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels48_8_msa;
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c->put_hevc_qpel_uni_w[9][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels64_8_msa;
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c->put_hevc_qpel_uni_w[1][0][1] = ff_hevc_put_hevc_uni_w_qpel_h4_8_msa;
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c->put_hevc_qpel_uni_w[3][0][1] = ff_hevc_put_hevc_uni_w_qpel_h8_8_msa;
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c->put_hevc_qpel_uni_w[4][0][1] = ff_hevc_put_hevc_uni_w_qpel_h12_8_msa;
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c->put_hevc_qpel_uni_w[5][0][1] = ff_hevc_put_hevc_uni_w_qpel_h16_8_msa;
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c->put_hevc_qpel_uni_w[6][0][1] = ff_hevc_put_hevc_uni_w_qpel_h24_8_msa;
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c->put_hevc_qpel_uni_w[7][0][1] = ff_hevc_put_hevc_uni_w_qpel_h32_8_msa;
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c->put_hevc_qpel_uni_w[8][0][1] = ff_hevc_put_hevc_uni_w_qpel_h48_8_msa;
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c->put_hevc_qpel_uni_w[9][0][1] = ff_hevc_put_hevc_uni_w_qpel_h64_8_msa;
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c->put_hevc_qpel_uni_w[1][1][0] = ff_hevc_put_hevc_uni_w_qpel_v4_8_msa;
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c->put_hevc_qpel_uni_w[3][1][0] = ff_hevc_put_hevc_uni_w_qpel_v8_8_msa;
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c->put_hevc_qpel_uni_w[4][1][0] = ff_hevc_put_hevc_uni_w_qpel_v12_8_msa;
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c->put_hevc_qpel_uni_w[5][1][0] = ff_hevc_put_hevc_uni_w_qpel_v16_8_msa;
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c->put_hevc_qpel_uni_w[6][1][0] = ff_hevc_put_hevc_uni_w_qpel_v24_8_msa;
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c->put_hevc_qpel_uni_w[7][1][0] = ff_hevc_put_hevc_uni_w_qpel_v32_8_msa;
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c->put_hevc_qpel_uni_w[8][1][0] = ff_hevc_put_hevc_uni_w_qpel_v48_8_msa;
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c->put_hevc_qpel_uni_w[9][1][0] = ff_hevc_put_hevc_uni_w_qpel_v64_8_msa;
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c->put_hevc_qpel_uni_w[1][1][1] = ff_hevc_put_hevc_uni_w_qpel_hv4_8_msa;
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c->put_hevc_qpel_uni_w[3][1][1] = ff_hevc_put_hevc_uni_w_qpel_hv8_8_msa;
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c->put_hevc_qpel_uni_w[4][1][1] =
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ff_hevc_put_hevc_uni_w_qpel_hv12_8_msa;
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c->put_hevc_qpel_uni_w[5][1][1] =
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ff_hevc_put_hevc_uni_w_qpel_hv16_8_msa;
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c->put_hevc_qpel_uni_w[6][1][1] =
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ff_hevc_put_hevc_uni_w_qpel_hv24_8_msa;
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c->put_hevc_qpel_uni_w[7][1][1] =
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ff_hevc_put_hevc_uni_w_qpel_hv32_8_msa;
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c->put_hevc_qpel_uni_w[8][1][1] =
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ff_hevc_put_hevc_uni_w_qpel_hv48_8_msa;
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c->put_hevc_qpel_uni_w[9][1][1] =
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ff_hevc_put_hevc_uni_w_qpel_hv64_8_msa;
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c->put_hevc_epel_uni_w[1][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels4_8_msa;
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c->put_hevc_epel_uni_w[2][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels6_8_msa;
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c->put_hevc_epel_uni_w[3][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels8_8_msa;
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c->put_hevc_epel_uni_w[4][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels12_8_msa;
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c->put_hevc_epel_uni_w[5][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels16_8_msa;
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c->put_hevc_epel_uni_w[6][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels24_8_msa;
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c->put_hevc_epel_uni_w[7][0][0] =
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ff_hevc_put_hevc_uni_w_pel_pixels32_8_msa;
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c->put_hevc_epel_uni_w[1][0][1] = ff_hevc_put_hevc_uni_w_epel_h4_8_msa;
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c->put_hevc_epel_uni_w[2][0][1] = ff_hevc_put_hevc_uni_w_epel_h6_8_msa;
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c->put_hevc_epel_uni_w[3][0][1] = ff_hevc_put_hevc_uni_w_epel_h8_8_msa;
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c->put_hevc_epel_uni_w[4][0][1] = ff_hevc_put_hevc_uni_w_epel_h12_8_msa;
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c->put_hevc_epel_uni_w[5][0][1] = ff_hevc_put_hevc_uni_w_epel_h16_8_msa;
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c->put_hevc_epel_uni_w[6][0][1] = ff_hevc_put_hevc_uni_w_epel_h24_8_msa;
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c->put_hevc_epel_uni_w[7][0][1] = ff_hevc_put_hevc_uni_w_epel_h32_8_msa;
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c->put_hevc_epel_uni_w[1][1][0] = ff_hevc_put_hevc_uni_w_epel_v4_8_msa;
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c->put_hevc_epel_uni_w[2][1][0] = ff_hevc_put_hevc_uni_w_epel_v6_8_msa;
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c->put_hevc_epel_uni_w[3][1][0] = ff_hevc_put_hevc_uni_w_epel_v8_8_msa;
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c->put_hevc_epel_uni_w[4][1][0] = ff_hevc_put_hevc_uni_w_epel_v12_8_msa;
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c->put_hevc_epel_uni_w[5][1][0] = ff_hevc_put_hevc_uni_w_epel_v16_8_msa;
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c->put_hevc_epel_uni_w[6][1][0] = ff_hevc_put_hevc_uni_w_epel_v24_8_msa;
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c->put_hevc_epel_uni_w[7][1][0] = ff_hevc_put_hevc_uni_w_epel_v32_8_msa;
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c->put_hevc_epel_uni_w[1][1][1] = ff_hevc_put_hevc_uni_w_epel_hv4_8_msa;
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c->put_hevc_epel_uni_w[2][1][1] = ff_hevc_put_hevc_uni_w_epel_hv6_8_msa;
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c->put_hevc_epel_uni_w[3][1][1] = ff_hevc_put_hevc_uni_w_epel_hv8_8_msa;
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c->put_hevc_epel_uni_w[4][1][1] =
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ff_hevc_put_hevc_uni_w_epel_hv12_8_msa;
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c->put_hevc_epel_uni_w[5][1][1] =
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ff_hevc_put_hevc_uni_w_epel_hv16_8_msa;
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c->put_hevc_epel_uni_w[6][1][1] =
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ff_hevc_put_hevc_uni_w_epel_hv24_8_msa;
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c->put_hevc_epel_uni_w[7][1][1] =
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ff_hevc_put_hevc_uni_w_epel_hv32_8_msa;
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c->put_hevc_qpel_bi[1][0][0] = ff_hevc_put_hevc_bi_pel_pixels4_8_msa;
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c->put_hevc_qpel_bi[3][0][0] = ff_hevc_put_hevc_bi_pel_pixels8_8_msa;
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c->put_hevc_qpel_bi[4][0][0] = ff_hevc_put_hevc_bi_pel_pixels12_8_msa;
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@ -117,6 +117,90 @@ UNI_MC(qpel, hv, 64);
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#undef UNI_MC
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#define UNI_W_MC(PEL, DIR, WIDTH) \
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void ff_hevc_put_hevc_uni_w_##PEL##_##DIR####WIDTH##_8_msa(uint8_t *dst, \
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ptrdiff_t \
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dst_stride, \
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uint8_t *src, \
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ptrdiff_t \
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src_stride, \
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int height, \
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int denom, \
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int weight, \
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int offset, \
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intptr_t mx, \
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intptr_t my, \
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int width)
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UNI_W_MC(pel, pixels, 4);
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UNI_W_MC(pel, pixels, 6);
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UNI_W_MC(pel, pixels, 8);
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UNI_W_MC(pel, pixels, 12);
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UNI_W_MC(pel, pixels, 16);
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UNI_W_MC(pel, pixels, 24);
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UNI_W_MC(pel, pixels, 32);
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UNI_W_MC(pel, pixels, 48);
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UNI_W_MC(pel, pixels, 64);
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UNI_W_MC(qpel, h, 4);
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UNI_W_MC(qpel, h, 8);
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UNI_W_MC(qpel, h, 12);
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UNI_W_MC(qpel, h, 16);
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UNI_W_MC(qpel, h, 24);
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UNI_W_MC(qpel, h, 32);
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UNI_W_MC(qpel, h, 48);
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UNI_W_MC(qpel, h, 64);
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UNI_W_MC(qpel, v, 4);
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UNI_W_MC(qpel, v, 8);
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UNI_W_MC(qpel, v, 12);
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UNI_W_MC(qpel, v, 16);
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UNI_W_MC(qpel, v, 24);
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UNI_W_MC(qpel, v, 32);
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UNI_W_MC(qpel, v, 48);
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UNI_W_MC(qpel, v, 64);
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UNI_W_MC(qpel, hv, 4);
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UNI_W_MC(qpel, hv, 8);
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UNI_W_MC(qpel, hv, 12);
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UNI_W_MC(qpel, hv, 16);
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UNI_W_MC(qpel, hv, 24);
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UNI_W_MC(qpel, hv, 32);
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UNI_W_MC(qpel, hv, 48);
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UNI_W_MC(qpel, hv, 64);
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UNI_W_MC(epel, h, 4);
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UNI_W_MC(epel, h, 6);
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UNI_W_MC(epel, h, 8);
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UNI_W_MC(epel, h, 12);
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UNI_W_MC(epel, h, 16);
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UNI_W_MC(epel, h, 24);
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UNI_W_MC(epel, h, 32);
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UNI_W_MC(epel, h, 48);
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UNI_W_MC(epel, h, 64);
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UNI_W_MC(epel, v, 4);
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UNI_W_MC(epel, v, 6);
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UNI_W_MC(epel, v, 8);
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UNI_W_MC(epel, v, 12);
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UNI_W_MC(epel, v, 16);
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UNI_W_MC(epel, v, 24);
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UNI_W_MC(epel, v, 32);
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UNI_W_MC(epel, v, 48);
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UNI_W_MC(epel, v, 64);
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UNI_W_MC(epel, hv, 4);
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UNI_W_MC(epel, hv, 6);
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UNI_W_MC(epel, hv, 8);
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UNI_W_MC(epel, hv, 12);
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UNI_W_MC(epel, hv, 16);
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UNI_W_MC(epel, hv, 24);
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UNI_W_MC(epel, hv, 32);
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UNI_W_MC(epel, hv, 48);
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UNI_W_MC(epel, hv, 64);
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#undef UNI_W_MC
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#define BI_MC(PEL, DIR, WIDTH) \
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void ff_hevc_put_hevc_bi_##PEL##_##DIR####WIDTH##_8_msa(uint8_t *dst, \
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ptrdiff_t dst_stride, \
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@ -802,6 +802,34 @@
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}
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#define DOTP_SB4_SH(...) DOTP_SB4(v8i16, __VA_ARGS__)
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/* Description : Dot product of halfword vector elements
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Arguments : Inputs - mult0, mult1
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cnst0, cnst1
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Outputs - out0, out1
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Return Type - signed word
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Details : Signed halfword elements from mult0 are multiplied with
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signed halfword elements from cnst0 producing a result
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twice the size of input i.e. signed word.
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Then this multiplication results of adjacent odd-even elements
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are added together and stored to the out vector
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(2 signed word results)
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*/
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#define DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) \
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{ \
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out0 = (RTYPE) __msa_dotp_s_w((v8i16) mult0, (v8i16) cnst0); \
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out1 = (RTYPE) __msa_dotp_s_w((v8i16) mult1, (v8i16) cnst1); \
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}
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#define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS__)
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#define DOTP_SH4(RTYPE, mult0, mult1, mult2, mult3, \
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cnst0, cnst1, cnst2, cnst3, \
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out0, out1, out2, out3) \
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{ \
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DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1); \
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DOTP_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3); \
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}
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#define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)
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/* Description : Dot product & addition of byte vector elements
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Arguments : Inputs - mult0, mult1
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cnst0, cnst1
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@ -1017,6 +1045,7 @@
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out1 = (RTYPE) __msa_ilvl_h((v8i16) in2, (v8i16) in3); \
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}
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#define ILVL_H2_SH(...) ILVL_H2(v8i16, __VA_ARGS__)
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#define ILVL_H2_SW(...) ILVL_H2(v4i32, __VA_ARGS__)
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#define ILVL_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
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out0, out1, out2, out3) \
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@ -1088,6 +1117,7 @@
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out1 = (RTYPE) __msa_ilvr_h((v8i16) in2, (v8i16) in3); \
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}
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#define ILVR_H2_SH(...) ILVR_H2(v8i16, __VA_ARGS__)
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#define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__)
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#define ILVR_H3(RTYPE, in0, in1, in2, in3, in4, in5, out0, out1, out2) \
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{ \
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@ -1555,6 +1585,31 @@
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#define SRAR_H4_UH(...) SRAR_H4(v8u16, __VA_ARGS__)
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#define SRAR_H4_SH(...) SRAR_H4(v8i16, __VA_ARGS__)
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/* Description : Shift right arithmetic rounded words
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Arguments : Inputs - in0, in1, shift
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Outputs - in0, in1, (in place)
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Return Type - as per RTYPE
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Details : Each element of vector 'in0' is shifted right arithmetic by
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number of bits respective element holds in vector 'shift'.
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The last discarded bit is added to shifted value for rounding
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and the result is in place written to 'in0'
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Here, 'shift' is a vector passed in
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Similar for other pairs
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*/
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#define SRAR_W2(RTYPE, in0, in1, shift) \
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{ \
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in0 = (RTYPE) __msa_srar_w((v4i32) in0, (v4i32) shift); \
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in1 = (RTYPE) __msa_srar_w((v4i32) in1, (v4i32) shift); \
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}
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#define SRAR_W2_SW(...) SRAR_W2(v4i32, __VA_ARGS__)
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#define SRAR_W4(RTYPE, in0, in1, in2, in3, shift) \
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{ \
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SRAR_W2(RTYPE, in0, in1, shift) \
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SRAR_W2(RTYPE, in2, in3, shift) \
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}
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#define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__)
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|
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/* Description : Shift right arithmetic rounded (immediate)
|
||||
Arguments : Inputs - in0, in1, in2, in3, shift
|
||||
Outputs - in0, in1, in2, in3 (in place)
|
||||
@ -1616,6 +1671,23 @@
|
||||
MUL2(in4, in5, in6, in7, out2, out3); \
|
||||
}
|
||||
|
||||
/* Description : Addition of 2 pairs of vectors
|
||||
Arguments : Inputs - in0, in1, in2, in3
|
||||
Outputs - out0, out1
|
||||
Details : Each element from 2 pairs vectors is added and 2 results are
|
||||
produced
|
||||
*/
|
||||
#define ADD2(in0, in1, in2, in3, out0, out1) \
|
||||
{ \
|
||||
out0 = in0 + in1; \
|
||||
out1 = in2 + in3; \
|
||||
}
|
||||
#define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \
|
||||
{ \
|
||||
ADD2(in0, in1, in2, in3, out0, out1); \
|
||||
ADD2(in4, in5, in6, in7, out2, out3); \
|
||||
}
|
||||
|
||||
/* Description : Zero extend unsigned byte elements to halfword elements
|
||||
Arguments : Inputs - in (1 input unsigned byte vector)
|
||||
Outputs - out0, out1 (unsigned 2 halfword vectors)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user