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avcodec/x86/fdct: Remove obsolete MMX(EXT) functions
x64 always has MMX, MMXEXT, SSE and SSE2 and this means that some functions for MMX, MMXEXT and 3dnow are always overridden by other functions (unless one e.g. explicitly disables SSE2) for x64. So given that the only systems that benefit from these functions are truely ancient 32bit x86s they are removed. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
This commit is contained in:
Andreas Rheinhardt
parent
7284ab789d
commit
d402ec6be9
@ -58,12 +58,6 @@ PR_WRAP(avx)
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#endif
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static const struct algo fdct_tab_arch[] = {
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#if HAVE_MMX_INLINE
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{ "MMX", ff_fdct_mmx, FF_IDCT_PERM_NONE, AV_CPU_FLAG_MMX },
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#endif
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#if HAVE_MMXEXT_INLINE
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{ "MMXEXT", ff_fdct_mmxext, FF_IDCT_PERM_NONE, AV_CPU_FLAG_MMXEXT },
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#endif
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#if HAVE_SSE2_INLINE
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{ "SSE2", ff_fdct_sse2, FF_IDCT_PERM_NONE, AV_CPU_FLAG_SSE2 },
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#endif
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@ -37,7 +37,7 @@
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#include "libavutil/x86/asm.h"
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#include "fdct.h"
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#if HAVE_MMX_INLINE
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#if HAVE_SSE2_INLINE
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//////////////////////////////////////////////////////////////////////
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//
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@ -71,8 +71,6 @@ DECLARE_ALIGNED(16, static const int16_t, ocos_4_16)[8] = {
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DECLARE_ALIGNED(16, static const int16_t, fdct_one_corr)[8] = { X8(1) };
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DECLARE_ALIGNED(8, static const int32_t, fdct_r_row)[2] = {RND_FRW_ROW, RND_FRW_ROW };
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static const struct
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{
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DECLARE_ALIGNED(16, const int32_t, fdct_r_row_sse2)[4];
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@ -82,80 +80,6 @@ static const struct
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}};
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//DECLARE_ALIGNED(16, static const long, fdct_r_row_sse2)[4] = {RND_FRW_ROW, RND_FRW_ROW, RND_FRW_ROW, RND_FRW_ROW};
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DECLARE_ALIGNED(8, static const int16_t, tab_frw_01234567)[] = { // forward_dct coeff table
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16384, 16384, 22725, 19266,
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16384, 16384, 12873, 4520,
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21407, 8867, 19266, -4520,
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-8867, -21407, -22725, -12873,
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16384, -16384, 12873, -22725,
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-16384, 16384, 4520, 19266,
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8867, -21407, 4520, -12873,
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21407, -8867, 19266, -22725,
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22725, 22725, 31521, 26722,
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22725, 22725, 17855, 6270,
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29692, 12299, 26722, -6270,
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-12299, -29692, -31521, -17855,
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22725, -22725, 17855, -31521,
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-22725, 22725, 6270, 26722,
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12299, -29692, 6270, -17855,
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29692, -12299, 26722, -31521,
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21407, 21407, 29692, 25172,
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21407, 21407, 16819, 5906,
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27969, 11585, 25172, -5906,
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-11585, -27969, -29692, -16819,
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21407, -21407, 16819, -29692,
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-21407, 21407, 5906, 25172,
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11585, -27969, 5906, -16819,
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27969, -11585, 25172, -29692,
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19266, 19266, 26722, 22654,
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19266, 19266, 15137, 5315,
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25172, 10426, 22654, -5315,
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-10426, -25172, -26722, -15137,
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19266, -19266, 15137, -26722,
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-19266, 19266, 5315, 22654,
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10426, -25172, 5315, -15137,
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25172, -10426, 22654, -26722,
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16384, 16384, 22725, 19266,
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16384, 16384, 12873, 4520,
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21407, 8867, 19266, -4520,
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-8867, -21407, -22725, -12873,
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16384, -16384, 12873, -22725,
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-16384, 16384, 4520, 19266,
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8867, -21407, 4520, -12873,
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21407, -8867, 19266, -22725,
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19266, 19266, 26722, 22654,
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19266, 19266, 15137, 5315,
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25172, 10426, 22654, -5315,
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-10426, -25172, -26722, -15137,
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19266, -19266, 15137, -26722,
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-19266, 19266, 5315, 22654,
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10426, -25172, 5315, -15137,
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25172, -10426, 22654, -26722,
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21407, 21407, 29692, 25172,
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21407, 21407, 16819, 5906,
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27969, 11585, 25172, -5906,
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-11585, -27969, -29692, -16819,
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21407, -21407, 16819, -29692,
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-21407, 21407, 5906, 25172,
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11585, -27969, 5906, -16819,
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27969, -11585, 25172, -29692,
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22725, 22725, 31521, 26722,
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22725, 22725, 17855, 6270,
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29692, 12299, 26722, -6270,
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-12299, -29692, -31521, -17855,
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22725, -22725, 17855, -31521,
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-22725, 22725, 6270, 26722,
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12299, -29692, 6270, -17855,
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29692, -12299, 26722, -31521,
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};
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static const struct
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{
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DECLARE_ALIGNED(16, const int16_t, tab_frw_01234567_sse2)[256];
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@ -375,7 +299,6 @@ static av_always_inline void fdct_col_##cpu(const int16_t *in, int16_t *out, int
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"r" (out + offset), "r" (ocos_4_16)); \
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}
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FDCT_COL(mmx, mm, movq)
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FDCT_COL(sse2, xmm, movdqa)
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static av_always_inline void fdct_row_sse2(const int16_t *in, int16_t *out)
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@ -443,148 +366,6 @@ static av_always_inline void fdct_row_sse2(const int16_t *in, int16_t *out)
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);
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}
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static av_always_inline void fdct_row_mmxext(const int16_t *in, int16_t *out,
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const int16_t *table)
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{
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__asm__ volatile (
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"pshufw $0x1B, 8(%0), %%mm5 \n\t"
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"movq (%0), %%mm0 \n\t"
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"movq %%mm0, %%mm1 \n\t"
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"paddsw %%mm5, %%mm0 \n\t"
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"psubsw %%mm5, %%mm1 \n\t"
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"movq %%mm0, %%mm2 \n\t"
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"punpckldq %%mm1, %%mm0 \n\t"
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"punpckhdq %%mm1, %%mm2 \n\t"
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"movq (%1), %%mm1 \n\t"
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"movq 8(%1), %%mm3 \n\t"
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"movq 16(%1), %%mm4 \n\t"
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"movq 24(%1), %%mm5 \n\t"
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"movq 32(%1), %%mm6 \n\t"
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"movq 40(%1), %%mm7 \n\t"
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"pmaddwd %%mm0, %%mm1 \n\t"
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"pmaddwd %%mm2, %%mm3 \n\t"
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"pmaddwd %%mm0, %%mm4 \n\t"
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"pmaddwd %%mm2, %%mm5 \n\t"
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"pmaddwd %%mm0, %%mm6 \n\t"
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"pmaddwd %%mm2, %%mm7 \n\t"
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"pmaddwd 48(%1), %%mm0 \n\t"
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"pmaddwd 56(%1), %%mm2 \n\t"
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"paddd %%mm1, %%mm3 \n\t"
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"paddd %%mm4, %%mm5 \n\t"
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"paddd %%mm6, %%mm7 \n\t"
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"paddd %%mm0, %%mm2 \n\t"
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"movq (%2), %%mm0 \n\t"
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"paddd %%mm0, %%mm3 \n\t"
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"paddd %%mm0, %%mm5 \n\t"
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"paddd %%mm0, %%mm7 \n\t"
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"paddd %%mm0, %%mm2 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm3 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm5 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm7 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm2 \n\t"
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"packssdw %%mm5, %%mm3 \n\t"
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"packssdw %%mm2, %%mm7 \n\t"
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"movq %%mm3, (%3) \n\t"
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"movq %%mm7, 8(%3) \n\t"
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:
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: "r" (in), "r" (table), "r" (fdct_r_row), "r" (out));
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}
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static av_always_inline void fdct_row_mmx(const int16_t *in, int16_t *out, const int16_t *table)
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{
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//FIXME reorder (I do not have an old MMX-only CPU here to benchmark ...)
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__asm__ volatile(
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"movd 12(%0), %%mm1 \n\t"
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"punpcklwd 8(%0), %%mm1 \n\t"
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"movq %%mm1, %%mm2 \n\t"
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"psrlq $0x20, %%mm1 \n\t"
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"movq 0(%0), %%mm0 \n\t"
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"punpcklwd %%mm2, %%mm1 \n\t"
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"movq %%mm0, %%mm5 \n\t"
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"paddsw %%mm1, %%mm0 \n\t"
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"psubsw %%mm1, %%mm5 \n\t"
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"movq %%mm0, %%mm2 \n\t"
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"punpckldq %%mm5, %%mm0 \n\t"
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"punpckhdq %%mm5, %%mm2 \n\t"
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"movq 0(%1), %%mm1 \n\t"
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"movq 8(%1), %%mm3 \n\t"
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"movq 16(%1), %%mm4 \n\t"
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"movq 24(%1), %%mm5 \n\t"
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"movq 32(%1), %%mm6 \n\t"
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"movq 40(%1), %%mm7 \n\t"
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"pmaddwd %%mm0, %%mm1 \n\t"
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"pmaddwd %%mm2, %%mm3 \n\t"
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"pmaddwd %%mm0, %%mm4 \n\t"
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"pmaddwd %%mm2, %%mm5 \n\t"
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"pmaddwd %%mm0, %%mm6 \n\t"
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"pmaddwd %%mm2, %%mm7 \n\t"
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"pmaddwd 48(%1), %%mm0 \n\t"
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"pmaddwd 56(%1), %%mm2 \n\t"
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"paddd %%mm1, %%mm3 \n\t"
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"paddd %%mm4, %%mm5 \n\t"
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"paddd %%mm6, %%mm7 \n\t"
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"paddd %%mm0, %%mm2 \n\t"
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"movq (%2), %%mm0 \n\t"
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"paddd %%mm0, %%mm3 \n\t"
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"paddd %%mm0, %%mm5 \n\t"
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"paddd %%mm0, %%mm7 \n\t"
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"paddd %%mm0, %%mm2 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm3 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm5 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm7 \n\t"
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"psrad $"S(SHIFT_FRW_ROW)", %%mm2 \n\t"
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"packssdw %%mm5, %%mm3 \n\t"
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"packssdw %%mm2, %%mm7 \n\t"
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"movq %%mm3, 0(%3) \n\t"
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"movq %%mm7, 8(%3) \n\t"
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:
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: "r" (in), "r" (table), "r" (fdct_r_row), "r" (out));
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}
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void ff_fdct_mmx(int16_t *block)
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{
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DECLARE_ALIGNED(8, int64_t, align_tmp)[16];
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int16_t * block1= (int16_t*)align_tmp;
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const int16_t *table= tab_frw_01234567;
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int i;
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fdct_col_mmx(block, block1, 0);
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fdct_col_mmx(block, block1, 4);
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for(i=8;i>0;i--) {
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fdct_row_mmx(block1, block, table);
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block1 += 8;
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table += 32;
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block += 8;
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}
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}
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#endif /* HAVE_MMX_INLINE */
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#if HAVE_MMXEXT_INLINE
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void ff_fdct_mmxext(int16_t *block)
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{
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DECLARE_ALIGNED(8, int64_t, align_tmp)[16];
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int16_t *block1= (int16_t*)align_tmp;
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const int16_t *table= tab_frw_01234567;
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int i;
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fdct_col_mmx(block, block1, 0);
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fdct_col_mmx(block, block1, 4);
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for(i=8;i>0;i--) {
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fdct_row_mmxext(block1, block, table);
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block1 += 8;
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table += 32;
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block += 8;
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}
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}
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#endif /* HAVE_MMXEXT_INLINE */
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#if HAVE_SSE2_INLINE
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void ff_fdct_sse2(int16_t *block)
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{
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DECLARE_ALIGNED(16, int64_t, align_tmp)[16];
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@ -21,8 +21,6 @@
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#include <stdint.h>
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void ff_fdct_mmx(int16_t *block);
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void ff_fdct_mmxext(int16_t *block);
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void ff_fdct_sse2(int16_t *block);
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#endif /* AVCODEC_X86_FDCT_H */
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@ -31,12 +31,6 @@ av_cold void ff_fdctdsp_init_x86(FDCTDSPContext *c, AVCodecContext *avctx,
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if (!high_bit_depth) {
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if ((dct_algo == FF_DCT_AUTO || dct_algo == FF_DCT_MMX)) {
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if (INLINE_MMX(cpu_flags))
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c->fdct = ff_fdct_mmx;
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if (INLINE_MMXEXT(cpu_flags))
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c->fdct = ff_fdct_mmxext;
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if (INLINE_SSE2(cpu_flags))
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c->fdct = ff_fdct_sse2;
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}
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