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ffbuild: Refine MIPS handling
To enable runtime detection for MIPS, we need to refine ffbuild part to support buildding these feature together. Firstly, we fixed configure, let it probe native ability of toolchain to decide wether a feature can to be enabled, also clearly marked the conflictions between loongson2 & loongson3 and Release 6 & rest. Secondly, we compile MMI and MSA C sources with their own flags to ensure their flags won't pollute the whole program and generate illegal code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Shiyou Yin <yinshiyou-hf@loongson.cn> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
This commit is contained in:
Jiaxun Yang
Michael Niedermayer
parent
b61d3dfab0
commit
d57d6def73
184
configure
vendored
184
configure
vendored
@ -2554,7 +2554,7 @@ mips64r6_deps="mips"
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mipsfpu_deps="mips"
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mipsdsp_deps="mips"
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mipsdspr2_deps="mips"
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mmi_deps="mips"
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mmi_deps_any="loongson2 loongson3"
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msa_deps="mipsfpu"
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msa2_deps="msa"
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@ -5005,8 +5005,6 @@ elif enabled bfin; then
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elif enabled mips; then
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cpuflags="-march=$cpu"
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if [ "$cpu" != "generic" ]; then
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disable mips32r2
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disable mips32r5
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@ -5015,81 +5013,47 @@ elif enabled mips; then
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disable mips64r6
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disable loongson2
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disable loongson3
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disable mipsdsp
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disable mipsdspr2
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disable msa
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disable mmi
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cpuflags="-march=$cpu"
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case $cpu in
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24kc|24kf*|24kec|34kc|1004kc|24kef*|34kf*|1004kf*|74kc|74kf)
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# General ISA levels
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mips1|mips3)
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;;
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mips32r2)
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enable msa
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enable mips32r2
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disable msa
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;;
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p5600|i6400|p6600)
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disable mipsdsp
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disable mipsdspr2
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mips32r5)
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enable msa
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enable mips32r2
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enable mips32r5
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;;
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loongson*)
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enable loongson2
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mips64r2|mips64r5)
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enable msa
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enable mmi
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enable mips64r2
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enable loongson3
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enable local_aligned
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enable simd_align_16
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enable fast_64bit
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enable fast_clz
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enable fast_cmov
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enable fast_unaligned
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disable aligned_stack
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disable mipsdsp
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disable mipsdspr2
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# When gcc version less than 5.3.0, add -fno-expensive-optimizations flag.
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if [ $cc == gcc ]; then
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gcc_version=$(gcc -dumpversion)
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if [ "$(echo "$gcc_version 5.3.0" | tr " " "\n" | sort -rV | head -n 1)" == "$gcc_version" ]; then
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expensive_optimization_flag=""
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else
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expensive_optimization_flag="-fno-expensive-optimizations"
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fi
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fi
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case $cpu in
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loongson3*)
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cpuflags="-march=loongson3a -mhard-float $expensive_optimization_flag"
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;;
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loongson2e)
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cpuflags="-march=loongson2e -mhard-float $expensive_optimization_flag"
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;;
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loongson2f)
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cpuflags="-march=loongson2f -mhard-float $expensive_optimization_flag"
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;;
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esac
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;;
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*)
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# Unknown CPU. Disable everything.
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warn "unknown CPU. Disabling all MIPS optimizations."
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disable mipsfpu
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disable mipsdsp
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disable mipsdspr2
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disable msa
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disable mmi
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;;
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esac
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case $cpu in
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# Cores from MIPS(MTI)
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24kc)
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disable mipsfpu
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disable mipsdsp
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disable mipsdspr2
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enable mips32r2
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;;
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24kf*)
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disable mipsdsp
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disable mipsdspr2
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;;
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24kec|34kc|1004kc)
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disable mipsfpu
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disable mipsdspr2
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24kf*|24kec|34kc|74Kc|1004kc)
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enable mips32r2
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;;
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24kef*|34kf*|1004kf*)
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disable mipsdspr2
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;;
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74kc)
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disable mipsfpu
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enable mipsdsp
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enable mips32r2
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;;
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p5600)
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enable msa
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enable mips32r2
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enable mips32r5
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check_cflags "-mtune=p5600" && check_cflags "-msched-weight -mload-store-pairs -funroll-loops"
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;;
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@ -5101,9 +5065,53 @@ elif enabled mips; then
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enable mips64r6
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check_cflags "-mtune=p6600 -mabi=64" && check_cflags "-msched-weight -mload-store-pairs -funroll-loops" && check_ldflags "-mabi=64"
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;;
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# Cores from Loongson
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loongson2e|loongson2f|loongson3*)
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enable mmi
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enable local_aligned
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enable simd_align_16
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enable fast_64bit
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enable fast_clz
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enable fast_cmov
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enable fast_unaligned
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disable aligned_stack
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# When gcc version less than 5.3.0, add -fno-expensive-optimizations flag.
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if test "$cc_type" = "gcc"; then
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case $gcc_basever in
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2|2.*|3.*|4.*|5.0|5.1|5.2)
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expensive_optimization_flag="-fno-expensive-optimizations"
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;;
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*)
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expensive_optimization_flag=""
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;;
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esac
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fi
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case $cpu in
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loongson3*)
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enable loongson3
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enable msa
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cpuflags="-march=loongson3a -mhard-float $expensive_optimization_flag"
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;;
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loongson2e)
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enable loongson2
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cpuflags="-march=loongson2e -mhard-float $expensive_optimization_flag"
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;;
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loongson2f)
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enable loongson2
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cpuflags="-march=loongson2f -mhard-float $expensive_optimization_flag"
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;;
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esac
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;;
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*)
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warn "unknown MIPS CPU"
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;;
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esac
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else
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# We do not disable anything. Is up to the user to disable the unwanted features.
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disable mipsdsp
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disable mipsdspr2
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# Disable DSP stuff for generic CPU, it can't be detected at runtime.
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warn 'generic cpu selected'
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fi
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@ -5850,28 +5858,42 @@ EOF
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elif enabled mips; then
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enabled loongson2 && check_inline_asm loongson2 '"dmult.g $8, $9, $10"'
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enabled loongson3 && check_inline_asm loongson3 '"gsldxc1 $f0, 0($2, $3)"'
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enabled mmi && check_inline_asm mmi '"punpcklhw $f0, $f0, $f0"'
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# Enable minimum ISA based on selected options
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# Check toolchain ISA level
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if enabled mips64; then
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enabled mips64r6 && check_inline_asm_flags mips64r6 '"dlsa $0, $0, $0, 1"' '-mips64r6'
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enabled mips64r2 && check_inline_asm_flags mips64r2 '"dext $0, $0, 0, 1"' '-mips64r2'
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disabled mips64r6 && disabled mips64r2 && check_inline_asm_flags mips64r1 '"daddi $0, $0, 0"' '-mips64'
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enabled mips64r6 && check_inline_asm mips64r6 '"dlsa $0, $0, $0, 1"' &&
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disable mips64r2
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enabled mips64r2 && check_inline_asm mips64r2 '"dext $0, $0, 0, 1"'
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disable mips32r6 && disable mips32r5 && disable mips32r2
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else
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enabled mips32r6 && check_inline_asm_flags mips32r6 '"aui $0, $0, 0"' '-mips32r6'
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enabled mips32r5 && check_inline_asm_flags mips32r5 '"eretnc"' '-mips32r5'
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enabled mips32r2 && check_inline_asm_flags mips32r2 '"ext $0, $0, 0, 1"' '-mips32r2'
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disabled mips32r6 && disabled mips32r5 && disabled mips32r2 && check_inline_asm_flags mips32r1 '"addi $0, $0, 0"' '-mips32'
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enabled mips32r6 && check_inline_asm mips32r6 '"aui $0, $0, 0"' &&
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disable mips32r5 && disable mips32r2
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enabled mips32r5 && check_inline_asm mips32r5 '"eretnc"'
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enabled mips32r2 && check_inline_asm mips32r2 '"ext $0, $0, 0, 1"'
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disable mips64r6 && disable mips64r5 && disable mips64r2
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fi
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enabled mipsfpu && check_inline_asm_flags mipsfpu '"cvt.d.l $f0, $f2"' '-mhard-float'
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enabled mipsfpu && check_inline_asm mipsfpu '"cvt.d.l $f0, $f2"'
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enabled mipsfpu && (enabled mips32r5 || enabled mips32r6 || enabled mips64r6) && check_inline_asm_flags mipsfpu '"cvt.d.l $f0, $f1"' '-mfp64'
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enabled mipsfpu && enabled msa && check_inline_asm_flags msa '"addvi.b $w0, $w1, 1"' '-mmsa' && check_headers msa.h || disable msa
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enabled mipsdsp && check_inline_asm_flags mipsdsp '"addu.qb $t0, $t1, $t2"' '-mdsp'
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enabled mipsdspr2 && check_inline_asm_flags mipsdspr2 '"absq_s.qb $t0, $t1"' '-mdspr2'
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enabled msa && enabled msa2 && check_inline_asm_flags msa2 '"nxbits.any.b $w0, $w0"' '-mmsa2' && check_headers msa2.h || disable msa2
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# MSA and MSA2 can be detected at runtime so we supply extra flags here
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enabled mipsfpu && enabled msa && check_inline_asm msa '"addvi.b $w0, $w1, 1"' '-mmsa' && append MSAFLAGS '-mmsa'
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enabled msa && enabled msa2 && check_inline_asm msa2 '"nxbits.any.b $w0, $w0"' '-mmsa2' && append MSAFLAGS '-mmsa2'
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# loongson2 have no switch cflag so we can only probe toolchain ability
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enabled loongson2 && check_inline_asm loongson2 '"dmult.g $8, $9, $10"' && disable loongson3
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# loongson3 is paired with MMI
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enabled loongson3 && check_inline_asm loongson3 '"gsldxc1 $f0, 0($2, $3)"' '-mloongson-ext' && append MMIFLAGS '-mloongson-ext'
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# MMI can be detected at runtime too
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enabled mmi && check_inline_asm mmi '"punpcklhw $f0, $f0, $f0"' '-mloongson-mmi' && append MMIFLAGS '-mloongson-mmi'
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if enabled bigendian && enabled msa; then
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disable msa
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@ -7447,6 +7469,8 @@ LDSOFLAGS=$LDSOFLAGS
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SHFLAGS=$(echo $($ldflags_filter $SHFLAGS))
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ASMSTRIPFLAGS=$ASMSTRIPFLAGS
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X86ASMFLAGS=$X86ASMFLAGS
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MSAFLAGS=$MSAFLAGS
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MMIFLAGS=$MMIFLAGS
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BUILDSUF=$build_suffix
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PROGSSUF=$progs_suffix
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FULLNAME=$FULLNAME
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@ -44,7 +44,7 @@ LDFLAGS := $(ALLFFLIBS:%=$(LD_PATH)lib%) $(LDFLAGS)
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define COMPILE
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$(call $(1)DEP,$(1))
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$($(1)) $($(1)FLAGS) $($(1)_DEPFLAGS) $($(1)_C) $($(1)_O) $(patsubst $(SRC_PATH)/%,$(SRC_LINK)/%,$<)
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$($(1)) $($(1)FLAGS) $($(2)) $($(1)_DEPFLAGS) $($(1)_C) $($(1)_O) $(patsubst $(SRC_PATH)/%,$(SRC_LINK)/%,$<)
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endef
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COMPILE_C = $(call COMPILE,CC)
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@ -54,6 +54,14 @@ COMPILE_M = $(call COMPILE,OBJCC)
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COMPILE_X86ASM = $(call COMPILE,X86ASM)
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COMPILE_HOSTC = $(call COMPILE,HOSTCC)
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COMPILE_NVCC = $(call COMPILE,NVCC)
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COMPILE_MMI = $(call COMPILE,CC,MMIFLAGS)
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COMPILE_MSA = $(call COMPILE,CC,MSAFLAGS)
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%_mmi.o: %_mmi.c
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$(COMPILE_MMI)
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%_msa.o: %_msa.c
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$(COMPILE_MSA)
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%.o: %.c
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$(COMPILE_C)
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@ -71,6 +71,8 @@ MSA-OBJS-$(CONFIG_IDCTDSP) += mips/idctdsp_msa.o \
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MSA-OBJS-$(CONFIG_MPEGVIDEO) += mips/mpegvideo_msa.o
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MSA-OBJS-$(CONFIG_MPEGVIDEOENC) += mips/mpegvideoencdsp_msa.o
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MSA-OBJS-$(CONFIG_ME_CMP) += mips/me_cmp_msa.o
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MSA-OBJS-$(CONFIG_VC1_DECODER) += mips/vc1dsp_msa.o
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MMI-OBJS += mips/constants.o
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MMI-OBJS-$(CONFIG_H264DSP) += mips/h264dsp_mmi.o
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MMI-OBJS-$(CONFIG_H264CHROMA) += mips/h264chroma_mmi.o
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@ -89,4 +91,3 @@ MMI-OBJS-$(CONFIG_WMV2DSP) += mips/wmv2dsp_mmi.o
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MMI-OBJS-$(CONFIG_HEVC_DECODER) += mips/hevcdsp_mmi.o
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MMI-OBJS-$(CONFIG_VP3DSP) += mips/vp3dsp_idct_mmi.o
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MMI-OBJS-$(CONFIG_VP9_DECODER) += mips/vp9_mc_mmi.o
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MSA-OBJS-$(CONFIG_VC1_DECODER) += mips/vc1dsp_msa.o
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