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Code Issues Releases Activity

lavu/floatdsp: RISC-V V vector_dmul

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Rémi Denis-Courmont 2022-09-26 17:52:31 +03:00 committed by Lynne
parent 7058af9969
commit da169a210d
2 changed files with 22 additions and 1 deletions
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6
libavutil/riscv/float_dsp_init.c
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@ -30,6 +30,8 @@ void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
int len);
void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
int len);
void ff_vector_dmul_scalar_rvv(double *dst, const double *src, double mul,
int len);
@ -43,7 +45,9 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
}
if (flags & AV_CPU_FLAG_RVV_F64)
if (flags & AV_CPU_FLAG_RVV_F64) {
fdsp->vector_dmul = ff_vector_dmul_rvv;
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
}
#endif
}

17
libavutil/riscv/float_dsp_rvv.S
View File

@ -55,6 +55,23 @@ NOHWF mv a2, a3
ret
endfunc
// (a0) = (a1) * (a2) [0..a3-1]
func ff_vector_dmul_rvv, zve64d
1:
vsetvli t0, a3, e64, m1, ta, ma
vle64.v v16, (a1)
sub a3, a3, t0
vle64.v v24, (a2)
sh3add a1, t0, a1
vfmul.vv v16, v16, v24
sh3add a2, t0, a2
vse64.v v16, (a0)
sh3add a0, t0, a0
bnez a3, 1b
ret
endfunc
// (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_dmul_scalar_rvv, zve64d
NOHWD fmv.d.x fa0, a2