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Use pextrw for SSE4 mbedge filter result writing, speedup 5-10cycles on
CPUs supporting it. Originally committed as revision 24437 to svn://svn.ffmpeg.org/ffmpeg/trunk
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@ -247,6 +247,7 @@ DECLARE_LOOP_FILTER(mmx)
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DECLARE_LOOP_FILTER(mmxext)
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DECLARE_LOOP_FILTER(sse2)
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DECLARE_LOOP_FILTER(ssse3)
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DECLARE_LOOP_FILTER(sse4)
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#endif
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@ -379,6 +380,9 @@ av_cold void ff_vp8dsp_init_x86(VP8DSPContext* c)
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if (mm_flags & FF_MM_SSE4) {
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c->vp8_idct_dc_add = ff_vp8_idct_dc_add_sse4;
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c->vp8_h_loop_filter16y = ff_vp8_h_loop_filter16y_mbedge_sse4;
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c->vp8_h_loop_filter8uv = ff_vp8_h_loop_filter8uv_mbedge_sse4;
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}
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#endif
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}
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@ -1932,10 +1932,24 @@ INNER_LOOPFILTER ssse3, h, 6, 8, 13
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; write 4 or 8 words in the mmx/xmm registers as 8 lines
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; 1 and 2 are the registers to write, this can be the same (for SSE2)
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; for pre-SSE4:
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; 3 is a general-purpose register that we will clobber
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; for SSE4:
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; 3 is a pointer to the destination's 5th line
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; 4 is a pointer to the destination's 4th line
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; 5 is -stride and +stride
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%macro WRITE_8W 6
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; 5/6 is -stride and +stride
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; 7 is optimization string
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%macro WRITE_8W 7
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%ifidn %7, sse4
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pextrw [%4+%5*4], %1, 0
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pextrw [%3+%5*4], %1, 1
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pextrw [%4+%5*2], %1, 2
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pextrw [%4+%5 ], %1, 3
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pextrw [%4 ], %1, 4
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pextrw [%3 ], %1, 5
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pextrw [%3+%6 ], %1, 6
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pextrw [%3+%6*2], %1, 7
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%else
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movd %3, %1
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%if mmsize == 8
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punpckhdq %1, %1
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@ -1974,6 +1988,7 @@ INNER_LOOPFILTER ssse3, h, 6, 8, 13
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%if mmsize == 8
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add %4, %5
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%endif
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%endif
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%endmacro
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%macro MBEDGE_LOOPFILTER 5
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@ -2509,14 +2524,17 @@ cglobal vp8_%2_loop_filter16y_mbedge_%1, 5, %3, %5
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%if mmsize == 8 ; mmx/mmxext (h)
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WRITE_4x2D 1, 2, 3, 4, dst_reg, dst2_reg, mstride_reg, stride_reg
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add dst_reg, 4
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WRITE_8W m5, m6, dst2_reg, dst_reg, mstride_reg, stride_reg
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WRITE_8W m5, m6, dst2_reg, dst_reg, mstride_reg, stride_reg, %4
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%else ; sse2 (h)
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lea dst8_reg, [dst8_reg+mstride_reg+1]
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WRITE_4x4D 1, 2, 3, 4, dst_reg, dst2_reg, dst8_reg, mstride_reg, stride_reg, %4
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lea dst_reg, [dst2_reg+mstride_reg+4]
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lea dst8_reg, [dst8_reg+mstride_reg+4]
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WRITE_8W m5, m5, dst2_reg, dst_reg, mstride_reg, stride_reg
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WRITE_8W m6, m6, dst2_reg, dst8_reg, mstride_reg, stride_reg
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WRITE_8W m5, m5, dst2_reg, dst_reg, mstride_reg, stride_reg, %2
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%ifidn %2, sse4
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lea dst_reg, [dst8_reg+ stride_reg]
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%endif
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WRITE_8W m6, m6, dst2_reg, dst8_reg, mstride_reg, stride_reg, %2
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%endif
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%endif
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@ -2574,3 +2592,10 @@ MBEDGE_LOOPFILTER ssse3, h, 6, 16, 16
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%endif
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MBEDGE_LOOPFILTER ssse3, v, 6, 8, 16
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MBEDGE_LOOPFILTER ssse3, h, 6, 8, 16
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%ifdef m8
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MBEDGE_LOOPFILTER sse4, h, 5, 16, 16
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%else
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MBEDGE_LOOPFILTER sse4, h, 6, 16, 16
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%endif
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MBEDGE_LOOPFILTER sse4, h, 6, 8, 16
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