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x86: xvid_idct: merged idct_put SSE2 versions
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Christophe Gisquet
Michael Niedermayer
parent
8200575d84
commit
decd5193e1
@ -292,13 +292,13 @@ SECTION .text
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%define TAN3 xmm13
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%define TAN1 xmm14
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%else
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%define ROW0 [r0 + 0*16]
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%define ROW0 [BLOCK + 0*16]
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%define REG0 xmm4
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%define ROW2 [r0 + 2*16]
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%define ROW2 [BLOCK + 2*16]
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%define REG2 xmm4
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%define ROW4 [r0 + 4*16]
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%define ROW4 [BLOCK + 4*16]
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%define REG4 xmm6
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%define ROW6 [r0 + 6*16]
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%define ROW6 [BLOCK + 6*16]
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%define REG6 xmm6
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%define XMMS xmm2
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%define SREG2 xmm7
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@ -369,8 +369,71 @@ SECTION .text
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movdqa TAN1, [tan1]
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%endmacro
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%macro FIRST_HALF 2 ; %1=dct %2=type(normal,add,put)
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psraw xmm5, 6
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psraw REG0, 6
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psraw TAN3, 6
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psraw xmm3, 6
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; dct coeffs must still be written for AC prediction
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%if %2 == 0
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movdqa [%1+1*16], TAN3
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movdqa [%1+2*16], xmm3
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movdqa [%1+5*16], REG0
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movdqa [%1+6*16], xmm5
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%else
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; Must now load args as gprs are no longer used for masks
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; DEST is set to where address of dest was loaded
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%if ARCH_X86_32
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%xdefine DEST r2q ; BLOCK is r0, stride r1
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movifnidn DEST, destm
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movifnidn strideq, stridem
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%else
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%xdefine DEST r0q
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%endif
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lea r3q, [3*strideq]
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%if %2 == 1
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packuswb TAN3, xmm3
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packuswb xmm5, REG0
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movq [DEST + strideq], TAN3
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movhps [DEST + 2*strideq], TAN3
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; REG0 and TAN3 are now available (and likely used in second half)
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%else
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%warning Unimplemented
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%endif
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%endif
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%endmacro
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%macro SECOND_HALF 6 ; %1=dct %2=type(normal,add,put) 3-6: xmms
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psraw %3, 6
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psraw %4, 6
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psraw %5, 6
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psraw %6, 6
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; dct coeffs must still be written for AC prediction
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%if %2 == 0
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movdqa [%1+0*16], %3
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movdqa [%1+3*16], %5
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movdqa [%1+4*16], %6
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movdqa [%1+7*16], %4
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%elif %2 == 1
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packuswb %3, %5
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packuswb %6, %4
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; address of dest may have been loaded
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movq [DEST], %3
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movhps [DEST + r3q], %3
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lea DEST, [DEST + 4*strideq]
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movq [DEST], %6
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movhps [DEST + r3q], %6
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; and now write remainder of first half
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movq [DEST + 2*strideq], xmm5
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movhps [DEST + strideq], xmm5
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%elif %2 == 2
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%warning Unimplemented
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%endif
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%endmacro
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; IDCT pass on columns.
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%macro iLLM_PASS 1 ;dct
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%macro iLLM_PASS 2 ; %1=dct %2=type(normal,add,put)
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movdqa xmm1, TAN3
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movdqa xmm3, TAN1
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pmulhw TAN3, xmm4
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@ -407,7 +470,7 @@ SECTION .text
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psubsw xmm5, REG6
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MOV32 ROW0, REG0
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MOV32 ROW4, REG4
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MOV32 TAN1, [r0]
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MOV32 TAN1, [BLOCK]
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movdqa XMMS, REG0
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psubsw REG0, REG4
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paddsw REG4, XMMS
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@ -423,33 +486,22 @@ SECTION .text
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movdqa XMMS, REG0
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psubsw REG0, xmm3
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paddsw xmm3, XMMS
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MOV32 [r0], TAN1
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psraw xmm5, 6
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psraw REG0, 6
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psraw TAN3, 6
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psraw xmm3, 6
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movdqa [%1+1*16], TAN3
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movdqa [%1+2*16], xmm3
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movdqa [%1+5*16], REG0
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movdqa [%1+6*16], xmm5
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MOV32 [BLOCK], TAN1
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FIRST_HALF %1, %2
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movdqa xmm0, xmm7
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movdqa xmm4, REG4
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psubsw xmm7, xmm1
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psubsw REG4, TAN1
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paddsw xmm1, xmm0
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paddsw TAN1, xmm4
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psraw xmm1, 6
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psraw xmm7, 6
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psraw TAN1, 6
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psraw REG4, 6
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movdqa [%1+0*16], xmm1
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movdqa [%1+3*16], TAN1
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movdqa [%1+4*16], REG4
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movdqa [%1+7*16], xmm7
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SECOND_HALF %1, %2, xmm1, xmm7, TAN1, REG4
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%endmacro
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; IDCT pass on columns, assuming rows 4-7 are zero
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%macro iLLM_PASS_SPARSE 1 ;dct
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%macro iLLM_PASS_SPARSE 2 ; %1=dct %2=type(normal,put,add)
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pmulhw TAN3, xmm4
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paddsw TAN3, xmm4
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movdqa xmm3, xmm6
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@ -475,7 +527,7 @@ SECTION .text
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movdqa xmm6, REG0
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psubsw xmm6, SREG2
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paddsw SREG2, REG0
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MOV32 TAN1, [r0]
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MOV32 TAN1, [BLOCK]
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movdqa XMMS, REG0
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psubsw REG0, xmm5
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paddsw xmm5, XMMS
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@ -485,70 +537,92 @@ SECTION .text
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movdqa XMMS, REG0
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psubsw REG0, xmm3
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paddsw xmm3, XMMS
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MOV32 [r0], TAN1
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psraw xmm5, 6
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psraw REG0, 6
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psraw TAN3, 6
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psraw xmm3, 6
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movdqa [%1+1*16], TAN3
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movdqa [%1+2*16], xmm3
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movdqa [%1+5*16], REG0
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movdqa [%1+6*16], xmm5
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MOV32 [BLOCK], TAN1
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FIRST_HALF %1, %2
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movdqa xmm0, SREG2
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movdqa xmm4, xmm6
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psubsw SREG2, xmm1
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psubsw xmm6, TAN1
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paddsw xmm1, xmm0
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paddsw TAN1, xmm4
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psraw xmm1, 6
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psraw SREG2, 6
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psraw TAN1, 6
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psraw xmm6, 6
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movdqa [%1+0*16], xmm1
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movdqa [%1+3*16], TAN1
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movdqa [%1+4*16], xmm6
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movdqa [%1+7*16], SREG2
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SECOND_HALF %1, %2, xmm1, SREG2, TAN1, xmm6
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%endmacro
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INIT_XMM sse2
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cglobal xvid_idct, 1, 5, 8+7*ARCH_X86_64, block
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%macro IDCT_SSE2 1 ; 0=normal 1=put 2=add
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%if %1 == 0 || ARCH_X86_32
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%define GPR0 r1d
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%define GPR1 r2d
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%define GPR2 r3d
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%define GPR3 r4d
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%define NUM_GPRS 5
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%else
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%define GPR0 r3d
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%define GPR1 r4d
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%define GPR2 r5d
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%define GPR3 r6d
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%define NUM_GPRS 7
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%endif
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%if %1 == 0
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cglobal xvid_idct, 1, NUM_GPRS, 8+7*ARCH_X86_64, block
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%xdefine BLOCK blockq
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%else
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%if %1 == 1
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cglobal xvid_idct_put, 0, NUM_GPRS, 8+7*ARCH_X86_64, dest, stride, block
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%else
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cglobal xvid_idct_add, 0, NUM_GPRS, 8+7*ARCH_X86_64, dest, stride, block
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%endif
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%if ARCH_X86_64
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%xdefine BLOCK blockq
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%else
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mov r0q, blockm
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%xdefine BLOCK r0q
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%endif
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%endif
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movq mm0, [pb_127]
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iMTX_MULT r0 + 0*16, iTab1, PUT_EVEN, ROW0, 0*16
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iMTX_MULT r0 + 1*16, iTab2, PUT_ODD, ROW1, 1*16
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iMTX_MULT r0 + 2*16, iTab3, PUT_EVEN, ROW2, 2*16
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iMTX_MULT BLOCK + 0*16, iTab1, PUT_EVEN, ROW0, 0*16
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iMTX_MULT BLOCK + 1*16, iTab2, PUT_ODD, ROW1, 1*16
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iMTX_MULT BLOCK + 2*16, iTab3, PUT_EVEN, ROW2, 2*16
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TEST_TWO_ROWS r0 + 3*16, r0 + 4*16, r1d, r2d, CLEAR_ODD, ROW3, CLEAR_EVEN, ROW4 ; a, c
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JZ r1d, col1
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iMTX_MULT r0 + 3*16, iTab4, PUT_ODD, ROW3, 3*16
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TEST_TWO_ROWS BLOCK + 3*16, BLOCK + 4*16, GPR0, GPR1, CLEAR_ODD, ROW3, CLEAR_EVEN, ROW4 ; a, c
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JZ GPR0, col1
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iMTX_MULT BLOCK + 3*16, iTab4, PUT_ODD, ROW3, 3*16
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.col1:
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TEST_TWO_ROWS r0 + 5*16, r0 + 6*16, r1d, r3d, CLEAR_ODD, ROW5, CLEAR_EVEN, ROW6 ; a, d
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TEST_ONE_ROW r0 + 7*16, r4d, CLEAR_ODD, ROW7 ; esi
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TEST_TWO_ROWS BLOCK + 5*16, BLOCK + 6*16, GPR0, GPR2, CLEAR_ODD, ROW5, CLEAR_EVEN, ROW6 ; a, d
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TEST_ONE_ROW BLOCK + 7*16, GPR3, CLEAR_ODD, ROW7 ; esi
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iLLM_HEAD
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JNZ r2d, 2
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JNZ r1d, 3
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JNZ r3d, 4
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JNZ r4d, 5
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iLLM_PASS_SPARSE r0
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JNZ GPR1, 2
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JNZ GPR0, 3
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JNZ GPR2, 4
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JNZ GPR3, 5
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iLLM_PASS_SPARSE BLOCK, %1
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jmp .6
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.2:
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iMTX_MULT r0 + 4*16, iTab1, PUT_EVEN, ROW4
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iMTX_MULT BLOCK + 4*16, iTab1, PUT_EVEN, ROW4
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.3:
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iMTX_MULT r0 + 5*16, iTab4, PUT_ODD, ROW5, 4*16
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JZ r3d, col2
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iMTX_MULT BLOCK + 5*16, iTab4, PUT_ODD, ROW5, 4*16
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JZ GPR2, col2
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.4:
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iMTX_MULT r0 + 6*16, iTab3, PUT_EVEN, ROW6, 5*16
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iMTX_MULT BLOCK + 6*16, iTab3, PUT_EVEN, ROW6, 5*16
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.col2:
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JZ r4d, col3
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JZ GPR3, col3
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.5:
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iMTX_MULT r0 + 7*16, iTab2, PUT_ODD, ROW7, 5*16
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iMTX_MULT BLOCK + 7*16, iTab2, PUT_ODD, ROW7, 5*16
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.col3:
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%if ARCH_X86_32
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iLLM_HEAD
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%endif
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iLLM_PASS r0
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iLLM_PASS BLOCK, %1
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.6:
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RET
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%endmacro
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INIT_XMM sse2
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IDCT_SSE2 0
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IDCT_SSE2 1
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%if ARCH_X86_32
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@ -26,11 +26,7 @@
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#include "idctdsp.h"
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#include "xvididct.h"
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static void xvid_idct_sse2_put(uint8_t *dest, int line_size, short *block)
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{
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ff_xvid_idct_sse2(block);
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ff_put_pixels_clamped(block, dest, line_size);
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}
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void ff_xvid_idct_put_sse2(uint8_t *dest, int line_size, short *block);
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static void xvid_idct_sse2_add(uint8_t *dest, int line_size, short *block)
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{
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@ -91,7 +87,7 @@ av_cold void ff_xvid_idct_init_x86(IDCTDSPContext *c, AVCodecContext *avctx,
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#endif
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if (EXTERNAL_SSE2(cpu_flags)) {
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c->idct_put = xvid_idct_sse2_put;
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c->idct_put = ff_xvid_idct_put_sse2;
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c->idct_add = xvid_idct_sse2_add;
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c->idct = ff_xvid_idct_sse2;
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c->perm_type = FF_IDCT_PERM_SSE2;
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