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Code Issues Releases Activity

lavu/floatdsp: RISC-V V vector_fmul_add

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Rémi Denis-Courmont 2022-09-26 17:52:34 +03:00 committed by Lynne
parent d120ab5b91
commit f4ea45040f
2 changed files with 22 additions and 0 deletions
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3
libavutil/riscv/float_dsp_init.c
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@ -31,6 +31,8 @@ void ff_vector_fmac_scalar_rvv(float *dst, const float *src, float mul,
int len);
void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
int len);
void ff_vector_fmul_add_rvv(float *dst, const float *src0, const float *src1,
const float *src2, int len);
void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1,
int len);
@ -48,6 +50,7 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
fdsp->vector_fmul = ff_vector_fmul_rvv;
fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_rvv;
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
fdsp->vector_fmul_add = ff_vector_fmul_add_rvv;
}
if (flags & AV_CPU_FLAG_RVV_F64) {

19
libavutil/riscv/float_dsp_rvv.S
View File

@ -74,6 +74,25 @@ NOHWF mv a2, a3
ret
endfunc
// (a0) = (a1) * (a2) + (a3) [0..a4-1]
func ff_vector_fmul_add_rvv, zve32f
1:
vsetvli t0, a4, e32, m1, ta, ma
vle32.v v8, (a1)
sub a4, a4, t0
vle32.v v16, (a2)
sh2add a1, t0, a1
vle32.v v24, (a3)
sh2add a2, t0, a2
vfmadd.vv v8, v16, v24
sh2add a3, t0, a3
vse32.v v8, (a0)
sh2add a0, t0, a0
bnez a4, 1b
ret
endfunc
// (a0) = (a1) * (a2) [0..a3-1]
func ff_vector_dmul_rvv, zve64d
1: