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vp9: minor refactorings in idct ssse3 assembly.
Make register usage in macros explicit; change mulsub_2w_4x to use 2 instead of 3 temp registers.
This commit is contained in:
Ronald S. Bultje
parent
8729964b99
commit
f9a0d4c6e0
@ -51,33 +51,32 @@ SECTION .text
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%macro VP9_MULSUB_2W_2X 6 ; dst1, dst2, src (unchanged), round, coefs1, coefs2
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pmaddwd m%1, m%3, %5
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pmaddwd m%2, m%3, %6
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paddd m%1, m%4
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paddd m%2, m%4
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psrad m%1, 14
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psrad m%2, 14
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paddd m%1, %4
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paddd m%2, %4
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psrad m%1, 14
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psrad m%2, 14
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%endmacro
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%macro VP9_UNPACK_MULSUB_2W_4X 4 ; dst1, dst2, coef1, coef2
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punpckhwd m6, m%2, m%1
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VP9_MULSUB_2W_2X 4, 5, 6, 7, [pw_m%3_%4], [pw_%4_%3]
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%macro VP9_UNPACK_MULSUB_2W_4X 7 ; dst1, dst2, coef1, coef2, rnd, tmp1, tmp2
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punpckhwd m%6, m%2, m%1
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VP9_MULSUB_2W_2X %7, %6, %6, %5, [pw_m%3_%4], [pw_%4_%3]
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punpcklwd m%2, m%1
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VP9_MULSUB_2W_2X %1, 6, %2, 7, [pw_m%3_%4], [pw_%4_%3]
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packssdw m%1, m4
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packssdw m6, m5
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SWAP %2, 6
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VP9_MULSUB_2W_2X %1, %2, %2, %5, [pw_m%3_%4], [pw_%4_%3]
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packssdw m%1, m%7
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packssdw m%2, m%6
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%endmacro
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%macro VP9_STORE_2X 2
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movh m6, [dstq]
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movh m7, [dstq+strideq]
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punpcklbw m6, m4
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punpcklbw m7, m4
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paddw m6, %1
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paddw m7, %2
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packuswb m6, m4
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packuswb m7, m4
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movh [dstq], m6
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movh [dstq+strideq], m7
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%macro VP9_STORE_2X 5 ; reg1, reg2, tmp1, tmp2, zero
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movh m%3, [dstq]
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movh m%4, [dstq+strideq]
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punpcklbw m%3, m%5
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punpcklbw m%4, m%5
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paddw m%3, m%1
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paddw m%4, m%2
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packuswb m%3, m%5
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packuswb m%4, m%5
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movh [dstq], m%3
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movh [dstq+strideq], m%4
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%endmacro
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;-------------------------------------------------------------------------------------------
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@ -95,7 +94,7 @@ SECTION .text
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mova m4, [pw_11585x2]
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pmulhrsw m2, m4 ; m2=t0
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pmulhrsw m0, m4 ; m0=t1
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VP9_UNPACK_MULSUB_2W_4X 1, 3, 15137, 6270 ; m1=t2, m3=t3
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VP9_UNPACK_MULSUB_2W_4X 1, 3, 15137, 6270, m7, 4, 5 ; m1=t2, m3=t3
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VP9_IDCT4_1D_FINALIZE
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%endmacro
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@ -113,11 +112,11 @@ SECTION .text
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mova m5, [pw_2048]
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pmulhrsw m0, m5 ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
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pmulhrsw m1, m5
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VP9_STORE_2X m0, m1
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VP9_STORE_2X 0, 1, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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pmulhrsw m2, m5
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pmulhrsw m3, m5
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VP9_STORE_2X m2, m3
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VP9_STORE_2X 2, 3, 6, 7, 4
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%endmacro
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INIT_MMX ssse3
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@ -136,11 +135,10 @@ cglobal vp9_idct_idct_4x4_add, 4,4,0, dst, stride, block, eob
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pshufw m0, m0, 0
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pxor m4, m4
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movh [blockq], m4
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mova m5, [pw_2048]
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pmulhrsw m0, m5 ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
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VP9_STORE_2X m0, m0
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pmulhrsw m0, [pw_2048] ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
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VP9_STORE_2X 0, 0, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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VP9_STORE_2X m0, m0
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VP9_STORE_2X 0, 0, 6, 7, 4
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RET
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; faster path for when only top left 2x2 block is set
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@ -194,9 +192,9 @@ cglobal vp9_idct_idct_4x4_add, 4,4,0, dst, stride, block, eob
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SUMSUB_BA w, 8, 0, 4 ; m8=IN(0)+IN(4) m0=IN(0)-IN(4)
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pmulhrsw m8, m12 ; m8=t0a
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pmulhrsw m0, m12 ; m0=t1a
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VP9_UNPACK_MULSUB_2W_4X 2, 10, 15137, 6270 ; m2=t2a, m10=t3a
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VP9_UNPACK_MULSUB_2W_4X 1, 11, 16069, 3196 ; m1=t4a, m11=t7a
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VP9_UNPACK_MULSUB_2W_4X 9, 3, 9102, 13623 ; m9=t5a, m3=t6a
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VP9_UNPACK_MULSUB_2W_4X 2, 10, 15137, 6270, m7, 4, 5 ; m2=t2a, m10=t3a
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VP9_UNPACK_MULSUB_2W_4X 1, 11, 16069, 3196, m7, 4, 5 ; m1=t4a, m11=t7a
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VP9_UNPACK_MULSUB_2W_4X 9, 3, 9102, 13623, m7, 4, 5 ; m9=t5a, m3=t6a
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SUMSUB_BA w, 10, 8, 4 ; m10=t0a+t3a (t0), m8=t0a-t3a (t3)
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SUMSUB_BA w, 2, 0, 4 ; m2=t1a+t2a (t1), m0=t1a-t2a (t2)
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SUMSUB_BA w, 9, 1, 4 ; m9=t4a+t5a (t4), m1=t4a-t5a (t5a)
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@ -232,19 +230,19 @@ cglobal vp9_idct_idct_4x4_add, 4,4,0, dst, stride, block, eob
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mova m5, [pw_1024]
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pmulhrsw m0, m5 ; (x*1024 + (1<<14))>>15 <=> (x+16)>>5
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pmulhrsw m1, m5
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VP9_STORE_2X m0, m1
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VP9_STORE_2X 0, 1, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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pmulhrsw m2, m5
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pmulhrsw m3, m5
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VP9_STORE_2X m2, m3
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VP9_STORE_2X 2, 3, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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pmulhrsw m8, m5
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pmulhrsw m9, m5
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VP9_STORE_2X m8, m9
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VP9_STORE_2X 8, 9, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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pmulhrsw m10, m5
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pmulhrsw m11, m5
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VP9_STORE_2X m10, m11
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VP9_STORE_2X 10, 11, 6, 7, 4
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%endmacro
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INIT_XMM ssse3
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@ -266,13 +264,13 @@ cglobal vp9_idct_idct_8x8_add, 4,4,13, dst, stride, block, eob
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movd [blockq], m4
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mova m5, [pw_1024]
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pmulhrsw m0, m5 ; (x*1024 + (1<<14))>>15 <=> (x+16)>>5
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VP9_STORE_2X m0, m0
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VP9_STORE_2X 0, 0, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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VP9_STORE_2X m0, m0
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VP9_STORE_2X 0, 0, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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VP9_STORE_2X m0, m0
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VP9_STORE_2X 0, 0, 6, 7, 4
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lea dstq, [dstq+2*strideq]
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VP9_STORE_2X m0, m0
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VP9_STORE_2X 0, 0, 6, 7, 4
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RET
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; faster path for when only left corner is set (3 input: DC, right to DC, below
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