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x86/vp9: inital AVX2 intra_pred
tos3k-vp9-b10000.webm on a Core i5-4200U @1.6GHz 1219 decicycles in ff_vp9_ipred_dc_32x32_ssse3, 131070 runs, 2 skips 439 decicycles in ff_vp9_ipred_dc_32x32_avx2, 131070 runs, 2 skips 3570 decicycles in ff_vp9_ipred_dc_top_32x32_ssse3, 4096 runs, 0 skips 2494 decicycles in ff_vp9_ipred_dc_top_32x32_avx2, 4096 runs, 0 skips 1419 decicycles in ff_vp9_ipred_dc_left_32x32_ssse3, 16384 runs, 0 skips 717 decicycles in ff_vp9_ipred_dc_left_32x32_avx2, 16384 runs, 0 skips 2737 decicycles in ff_vp9_ipred_tm_32x32_avx, 1024 runs, 0 skips 2088 decicycles in ff_vp9_ipred_tm_32x32_avx2, 1024 runs, 0 skips 3090 decicycles in ff_vp9_ipred_v_32x32_avx, 512 runs, 0 skips 2226 decicycles in ff_vp9_ipred_v_32x32_avx2, 512 runs, 0 skips 1565 decicycles in ff_vp9_ipred_h_32x32_avx, 1024 runs, 0 skips 922 decicycles in ff_vp9_ipred_h_32x32_avx2, 1024 runs, 0 skips Signed-off-by: James Almer <jamrial@gmail.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
James Almer
Michael Niedermayer
parent
5183fac92f
commit
fc8db12a73
@ -1,5 +1,5 @@
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/*
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* MMX/SSE constants used across x86 dsp optimizations.
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* MMX/SSE/AVX constants used across x86 dsp optimizations.
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*
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* This file is part of FFmpeg.
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*
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@ -47,7 +47,9 @@ DECLARE_ALIGNED(16, const xmm_reg, ff_pw_512) = { 0x0200020002000200ULL, 0x020
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_1019) = { 0x03FB03FB03FB03FBULL, 0x03FB03FB03FB03FBULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pb_0) = { 0x0000000000000000ULL, 0x0000000000000000ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pb_1) = { 0x0101010101010101ULL, 0x0101010101010101ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pb_3) = { 0x0303030303030303ULL, 0x0303030303030303ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pb_1) = { 0x0101010101010101ULL, 0x0101010101010101ULL,
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0x0101010101010101ULL, 0x0101010101010101ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pb_3) = { 0x0303030303030303ULL, 0x0303030303030303ULL,
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0x0303030303030303ULL, 0x0303030303030303ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pb_80) = { 0x8080808080808080ULL, 0x8080808080808080ULL };
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DECLARE_ALIGNED(8, const uint64_t, ff_pb_FC) = 0xFCFCFCFCFCFCFCFCULL;
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@ -44,8 +44,8 @@ extern const uint64_t ff_pw_96;
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extern const uint64_t ff_pw_128;
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extern const uint64_t ff_pw_255;
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extern const xmm_reg ff_pb_1;
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extern const xmm_reg ff_pb_3;
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extern const ymm_reg ff_pb_1;
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extern const ymm_reg ff_pb_3;
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extern const xmm_reg ff_pb_80;
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extern const xmm_reg ff_pb_F8;
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extern const uint64_t ff_pb_FC;
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@ -241,6 +241,13 @@ ipred_funcs(hd, ssse3, avx);
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ipred_funcs(vl, ssse3, avx);
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ipred_funcs(vr, ssse3, avx);
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ipred_func(32, dc, avx2);
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ipred_func(32, dc_left, avx2);
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ipred_func(32, dc_top, avx2);
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ipred_func(32, v, avx2);
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ipred_func(32, h, avx2);
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ipred_func(32, tm, avx2);
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#undef ipred_funcs
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#undef ipred_func_set
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#undef ipred_func
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@ -388,6 +395,15 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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init_ipred(TX_32X32, 32, avx);
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}
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if (EXTERNAL_AVX2(cpu_flags)) {
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dsp->intra_pred[TX_32X32][DC_PRED] = ff_vp9_ipred_dc_32x32_avx2;
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dsp->intra_pred[TX_32X32][LEFT_DC_PRED] = ff_vp9_ipred_dc_left_32x32_avx2;
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dsp->intra_pred[TX_32X32][TOP_DC_PRED] = ff_vp9_ipred_dc_top_32x32_avx2;
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dsp->intra_pred[TX_32X32][VERT_PRED] = ff_vp9_ipred_v_32x32_avx2;
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dsp->intra_pred[TX_32X32][HOR_PRED] = ff_vp9_ipred_h_32x32_avx2;
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dsp->intra_pred[TX_32X32][TM_VP8_PRED] = ff_vp9_ipred_tm_32x32_avx2;
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}
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#undef init_fpel
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#undef init_subpel1
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#undef init_subpel2
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@ -29,10 +29,10 @@
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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SECTION_RODATA 32
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pw_m256: times 8 dw -256
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pw_m255: times 8 dw -255
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pw_m256: times 16 dw -256
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pw_m255: times 16 dw -255
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pw_512: times 8 dw 512
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pw_1024: times 8 dw 1024
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pw_2048: times 8 dw 2048
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@ -72,7 +72,7 @@ pb_3to1_5x0: db 3, 2, 1
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times 9 db 0
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pb_Fto0: db 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
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pb_2: times 16 db 2
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pb_2: times 32 db 2
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pb_15: times 16 db 15
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cextern pb_1
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@ -180,6 +180,40 @@ cglobal vp9_ipred_dc_32x32, 4, 4, 5, dst, stride, l, a
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jg .loop
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RET
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_dc_32x32, 4, 4, 3, dst, stride, l, a
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mova m0, [lq]
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mova m1, [aq]
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DEFINE_ARGS dst, stride, stride3, cnt
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lea stride3q, [strideq*3]
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pxor m2, m2
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psadbw m0, m2
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psadbw m1, m2
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paddw m0, m1
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vextracti128 xm1, m0, 1
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paddw xm0, xm1
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movhlps xm1, xm0
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paddw xm0, xm1
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pmulhrsw xm0, [pw_512]
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vpbroadcastb m0, xm0
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mov cntd, 4
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.loop:
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m0
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mova [dstq+strideq*2], m0
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mova [dstq+stride3q ], m0
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lea dstq, [dstq+strideq*4]
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m0
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mova [dstq+strideq*2], m0
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mova [dstq+stride3q ], m0
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lea dstq, [dstq+strideq*4]
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dec cntd
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jg .loop
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RET
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%endif
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; dc_top/left_NxN(uint8_t *dst, ptrdiff_t stride, const uint8_t *l, const uint8_t *a)
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%macro DC_1D_FUNCS 2 ; dir (top or left), arg (a or l)
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@ -267,6 +301,37 @@ cglobal vp9_ipred_dc_%1_32x32, 4, 4, 3, dst, stride, l, a
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dec cntd
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jg .loop
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RET
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_dc_%1_32x32, 4, 4, 3, dst, stride, l, a
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mova m0, [%2q]
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DEFINE_ARGS dst, stride, stride3, cnt
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lea stride3q, [strideq*3]
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pxor m2, m2
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psadbw m0, m2
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vextracti128 xm1, m0, 1
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paddw xm0, xm1
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movhlps xm1, xm0
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paddw xm0, xm1
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pmulhrsw xm0, [pw_1024]
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vpbroadcastb m0, xm0
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mov cntd, 4
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.loop:
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m0
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mova [dstq+strideq*2], m0
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mova [dstq+stride3q ], m0
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lea dstq, [dstq+strideq*4]
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m0
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mova [dstq+strideq*2], m0
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mova [dstq+stride3q ], m0
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lea dstq, [dstq+strideq*4]
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dec cntd
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jg .loop
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RET
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%endif
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%endmacro
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DC_1D_FUNCS top, a
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@ -327,6 +392,29 @@ cglobal vp9_ipred_v_32x32, 4, 4, 2, dst, stride, l, a
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jg .loop
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RET
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_v_32x32, 4, 4, 1, dst, stride, l, a
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mova m0, [aq]
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DEFINE_ARGS dst, stride, stride3, cnt
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lea stride3q, [strideq*3]
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mov cntd, 4
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.loop:
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m0
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mova [dstq+strideq*2], m0
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mova [dstq+stride3q ], m0
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lea dstq, [dstq+strideq*4]
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m0
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mova [dstq+strideq*2], m0
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mova [dstq+stride3q ], m0
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lea dstq, [dstq+strideq*4]
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dec cntd
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jg .loop
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RET
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%endif
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; h
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INIT_XMM ssse3
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@ -417,6 +505,32 @@ cglobal vp9_ipred_h_32x32, 3, 5, 8, dst, stride, l, stride3, cnt
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H_XMM_FUNCS ssse3
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H_XMM_FUNCS avx
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_h_32x32, 3, 5, 8, dst, stride, l, stride3, cnt
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mova m5, [pb_1]
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mova m6, [pb_2]
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mova m7, [pb_3]
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pxor m4, m4
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lea stride3q, [strideq*3]
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mov cntq, 7
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.loop:
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movd xm3, [lq+cntq*4]
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vinserti128 m3, m3, xm3, 1
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pshufb m0, m3, m7
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pshufb m1, m3, m6
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mova [dstq+strideq*0], m0
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mova [dstq+strideq*1], m1
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pshufb m2, m3, m5
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pshufb m3, m4
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mova [dstq+strideq*2], m2
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mova [dstq+stride3q ], m3
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lea dstq, [dstq+strideq*4]
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dec cntq
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jge .loop
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RET
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%endif
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; tm
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INIT_MMX ssse3
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@ -554,6 +668,41 @@ cglobal vp9_ipred_tm_32x32, 4, 4, 14, dst, stride, l, a
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TM_XMM_FUNCS ssse3
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TM_XMM_FUNCS avx
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal vp9_ipred_tm_32x32, 4, 4, 8, dst, stride, l, a
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pxor m3, m3
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pinsrw xm2, [aq-1], 0
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vinserti128 m2, m2, xm2, 1
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mova m0, [aq]
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DEFINE_ARGS dst, stride, l, cnt
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mova m4, [pw_m256]
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mova m5, [pw_m255]
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pshufb m2, m4
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punpckhbw m1, m0, m3
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punpcklbw m0, m3
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psubw m1, m2
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psubw m0, m2
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mov cntq, 15
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.loop:
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pinsrw xm7, [lq+cntq*2], 0
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vinserti128 m7, m7, xm7, 1
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pshufb m3, m7, m5
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pshufb m7, m4
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paddw m2, m3, m0
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paddw m3, m1
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paddw m6, m7, m0
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paddw m7, m1
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packuswb m2, m3
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packuswb m6, m7
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mova [dstq+strideq*0], m2
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mova [dstq+strideq*1], m6
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lea dstq, [dstq+strideq*2]
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dec cntq
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jge .loop
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RET
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%endif
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; dl
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%macro LOWPASS 4 ; left [dst], center, right, tmp
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@ -25,6 +25,7 @@
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#include "config.h"
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typedef struct xmm_reg { uint64_t a, b; } xmm_reg;
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typedef struct ymm_reg { uint64_t a, b, c, d; } ymm_reg;
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#if ARCH_X86_64
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# define OPSIZE "q"
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