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updated mmx macros
Originally committed as revision 42 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Fabrice Bellard
parent
f33802a005
commit
fe97c87d65
@ -1,48 +1,14 @@
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/* mmx.h
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/*
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* mmx.h
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* Copyright (C) 1997-2001 H. Dietz and R. Fisher
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*/
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MultiMedia eXtensions GCC interface library for IA32.
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/*
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* The type of an value that fits in an MMX register (note that long
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* long constant values MUST be suffixed by LL and unsigned long long
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* values by ULL, lest they be truncated by the compiler)
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*/
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To use this library, simply include this header file
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and compile with GCC. You MUST have inlining enabled
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in order for mmx_ok() to work; this can be done by
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simply using -O on the GCC command line.
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Compiling with -DMMX_TRACE will cause detailed trace
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output to be sent to stderr for each mmx operation.
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This adds lots of code, and obviously slows execution to
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a crawl, but can be very useful for debugging.
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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AND FITNESS FOR ANY PARTICULAR PURPOSE.
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1997-99 by H. Dietz and R. Fisher
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Notes:
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It appears that the latest gas has the pand problem fixed, therefore
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I'll undefine BROKEN_PAND by default.
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*/
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#ifndef _MMX_H
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#define _MMX_H
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/* Warning: at this writing, the version of GAS packaged
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with most Linux distributions does not handle the
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parallel AND operation mnemonic correctly. If the
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symbol BROKEN_PAND is defined, a slower alternative
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coding will be used. If execution of mmxtest results
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in an illegal instruction fault, define this symbol.
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*/
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#undef BROKEN_PAND
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/* The type of an value that fits in an MMX register
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(note that long long constant values MUST be suffixed
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by LL and unsigned long long values by ULL, lest
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they be truncated by the compiler)
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*/
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typedef union {
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long long q; /* Quadword (64-bit) value */
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unsigned long long uq; /* Unsigned Quadword */
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@ -53,484 +19,221 @@ typedef union {
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char b[8]; /* 8 Byte (8-bit) values */
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unsigned char ub[8]; /* 8 Unsigned Byte */
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float s[2]; /* Single-precision (32-bit) value */
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} __attribute__ ((aligned (8))) mmx_t; /* On an 8-byte (64-bit) boundary */
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} mmx_t; /* On an 8-byte (64-bit) boundary */
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/* Helper functions for the instruction macros that follow...
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(note that memory-to-register, m2r, instructions are nearly
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as efficient as register-to-register, r2r, instructions;
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however, memory-to-memory instructions are really simulated
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as a convenience, and are only 1/3 as efficient)
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*/
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#ifdef MMX_TRACE
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/* Include the stuff for printing a trace to stderr...
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*/
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#include <stdio.h>
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#define mmx_i2r(op, imm, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace.uq = (imm); \
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fprintf(stderr, #op "_i2r(" #imm "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (imm)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_m2r(op, mem, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mem); \
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fprintf(stderr, #op "_m2r(" #mem "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (mem)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_r2m(op, reg, mem) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2m(" #reg "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=X" (mem) \
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: /* nothing */ ); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_r2r(op, regs, regd) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #regs ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2r(" #regs "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_m2m(op, mems, memd) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mems); \
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fprintf(stderr, #op "_m2m(" #mems "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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mmx_trace = (memd); \
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fprintf(stderr, #memd "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (memd) \
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: "X" (mems)); \
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mmx_trace = (memd); \
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fprintf(stderr, #memd "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#else
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/* These macros are a lot simpler without the tracing...
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*/
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#define mmx_i2r(op, imm, reg) \
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#define mmx_i2r(op,imm,reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "i" (imm) )
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#define mmx_m2r(op, mem, reg) \
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#define mmx_m2r(op,mem,reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "m" (mem))
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#define mmx_r2m(op, reg, mem) \
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#define mmx_r2m(op,reg,mem) \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=m" (mem) \
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: /* nothing */ )
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#define mmx_r2r(op, regs, regd) \
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#define mmx_r2r(op,regs,regd) \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd)
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#define mmx_m2m(op, mems, memd) \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=m" (memd) \
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: "m" (mems))
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#endif
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/* 1x64 MOVe Quadword
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(this is both a load and a store...
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in fact, it is the only way to store)
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*/
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#define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
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#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
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#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
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#define movq(vars, vard) \
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__asm__ __volatile__ ("movq %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 1x32 MOVe Doubleword
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(like movq, this is both load and store...
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but is most useful for moving things between
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mmx registers and ordinary registers)
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*/
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#define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
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#define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
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#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
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#define movd(vars, vard) \
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__asm__ __volatile__ ("movd %1, %%mm0\n\t" \
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"movd %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 2x32, 4x16, and 8x8 Parallel ADDs
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*/
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#define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
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#define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
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#define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
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#define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
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#define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
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#define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
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#define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
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#define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
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#define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
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/* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
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*/
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#define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
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#define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
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#define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
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#define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
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#define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
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#define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
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/* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
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*/
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#define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
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#define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
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#define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
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#define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
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#define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
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#define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel SUBs
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*/
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#define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
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#define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
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#define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
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#define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
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#define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
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#define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
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#define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
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#define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
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#define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
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/* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
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*/
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#define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
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#define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
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#define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
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#define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
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#define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
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#define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
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/* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
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*/
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#define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
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#define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
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#define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
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#define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
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#define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
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#define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
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/* 4x16 Parallel MULs giving Low 4x16 portions of results
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*/
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#define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
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#define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
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#define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
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/* 4x16 Parallel MULs giving High 4x16 portions of results
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*/
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#define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
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#define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
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#define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
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/* 4x16->2x32 Parallel Mul-ADD
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(muls like pmullw, then adds adjacent 16-bit fields
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in the multiply result to make the final 2x32 result)
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*/
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#define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
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#define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
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#define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
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/* 1x64 bitwise AND
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*/
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#ifdef BROKEN_PAND
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#define pand_m2r(var, reg) \
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{ \
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mmx_m2r(pandn, (mmx_t) -1LL, reg); \
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mmx_m2r(pandn, var, reg); \
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}
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#define pand_r2r(regs, regd) \
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{ \
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mmx_m2r(pandn, (mmx_t) -1LL, regd); \
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mmx_r2r(pandn, regs, regd) \
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}
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#define pand(vars, vard) \
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{ \
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movq_m2r(vard, mm0); \
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mmx_m2r(pandn, (mmx_t) -1LL, mm0); \
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mmx_m2r(pandn, vars, mm0); \
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movq_r2m(mm0, vard); \
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}
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#else
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#define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
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#define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
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#define pand(vars, vard) mmx_m2m(pand, vars, vard)
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#endif
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/* 1x64 bitwise AND with Not the destination
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*/
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#define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
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#define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
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#define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
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/* 1x64 bitwise OR
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*/
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#define por_m2r(var, reg) mmx_m2r(por, var, reg)
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#define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
|
||||
#define por(vars, vard) mmx_m2m(por, vars, vard)
|
||||
|
||||
|
||||
/* 1x64 bitwise eXclusive OR
|
||||
*/
|
||||
#define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
|
||||
#define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
|
||||
#define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
|
||||
|
||||
|
||||
/* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
|
||||
(resulting fields are either 0 or -1)
|
||||
*/
|
||||
#define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
|
||||
#define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
|
||||
#define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
|
||||
|
||||
#define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
|
||||
#define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
|
||||
#define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
|
||||
|
||||
#define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
|
||||
#define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
|
||||
#define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
|
||||
|
||||
|
||||
/* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
|
||||
(resulting fields are either 0 or -1)
|
||||
*/
|
||||
#define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
|
||||
#define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
|
||||
#define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
|
||||
|
||||
#define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
|
||||
#define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
|
||||
#define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
|
||||
|
||||
#define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
|
||||
#define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
|
||||
#define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
|
||||
|
||||
|
||||
/* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
|
||||
*/
|
||||
#define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
|
||||
#define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
|
||||
#define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
|
||||
#define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
|
||||
|
||||
#define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
|
||||
#define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
|
||||
#define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
|
||||
#define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
|
||||
|
||||
#define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
|
||||
#define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
|
||||
#define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
|
||||
#define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
|
||||
|
||||
|
||||
/* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
|
||||
*/
|
||||
#define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
|
||||
#define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
|
||||
#define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
|
||||
#define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
|
||||
|
||||
#define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
|
||||
#define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
|
||||
#define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
|
||||
#define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
|
||||
|
||||
#define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
|
||||
#define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
|
||||
#define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
|
||||
#define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
|
||||
|
||||
|
||||
/* 2x32 and 4x16 Parallel Shift Right Arithmetic
|
||||
*/
|
||||
#define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
|
||||
#define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
|
||||
#define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
|
||||
#define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
|
||||
|
||||
#define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
|
||||
#define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
|
||||
#define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
|
||||
#define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
|
||||
#define emms() __asm__ __volatile__ ("emms")
|
||||
|
||||
#define movd_m2r(var,reg) mmx_m2r (movd, var, reg)
|
||||
#define movd_r2m(reg,var) mmx_r2m (movd, reg, var)
|
||||
#define movd_r2r(regs,regd) mmx_r2r (movd, regs, regd)
|
||||
|
||||
#define movq_m2r(var,reg) mmx_m2r (movq, var, reg)
|
||||
#define movq_r2m(reg,var) mmx_r2m (movq, reg, var)
|
||||
#define movq_r2r(regs,regd) mmx_r2r (movq, regs, regd)
|
||||
|
||||
#define packssdw_m2r(var,reg) mmx_m2r (packssdw, var, reg)
|
||||
#define packssdw_r2r(regs,regd) mmx_r2r (packssdw, regs, regd)
|
||||
#define packsswb_m2r(var,reg) mmx_m2r (packsswb, var, reg)
|
||||
#define packsswb_r2r(regs,regd) mmx_r2r (packsswb, regs, regd)
|
||||
|
||||
#define packuswb_m2r(var,reg) mmx_m2r (packuswb, var, reg)
|
||||
#define packuswb_r2r(regs,regd) mmx_r2r (packuswb, regs, regd)
|
||||
|
||||
#define paddb_m2r(var,reg) mmx_m2r (paddb, var, reg)
|
||||
#define paddb_r2r(regs,regd) mmx_r2r (paddb, regs, regd)
|
||||
#define paddd_m2r(var,reg) mmx_m2r (paddd, var, reg)
|
||||
#define paddd_r2r(regs,regd) mmx_r2r (paddd, regs, regd)
|
||||
#define paddw_m2r(var,reg) mmx_m2r (paddw, var, reg)
|
||||
#define paddw_r2r(regs,regd) mmx_r2r (paddw, regs, regd)
|
||||
|
||||
#define paddsb_m2r(var,reg) mmx_m2r (paddsb, var, reg)
|
||||
#define paddsb_r2r(regs,regd) mmx_r2r (paddsb, regs, regd)
|
||||
#define paddsw_m2r(var,reg) mmx_m2r (paddsw, var, reg)
|
||||
#define paddsw_r2r(regs,regd) mmx_r2r (paddsw, regs, regd)
|
||||
|
||||
#define paddusb_m2r(var,reg) mmx_m2r (paddusb, var, reg)
|
||||
#define paddusb_r2r(regs,regd) mmx_r2r (paddusb, regs, regd)
|
||||
#define paddusw_m2r(var,reg) mmx_m2r (paddusw, var, reg)
|
||||
#define paddusw_r2r(regs,regd) mmx_r2r (paddusw, regs, regd)
|
||||
|
||||
#define pand_m2r(var,reg) mmx_m2r (pand, var, reg)
|
||||
#define pand_r2r(regs,regd) mmx_r2r (pand, regs, regd)
|
||||
|
||||
#define pandn_m2r(var,reg) mmx_m2r (pandn, var, reg)
|
||||
#define pandn_r2r(regs,regd) mmx_r2r (pandn, regs, regd)
|
||||
|
||||
#define pcmpeqb_m2r(var,reg) mmx_m2r (pcmpeqb, var, reg)
|
||||
#define pcmpeqb_r2r(regs,regd) mmx_r2r (pcmpeqb, regs, regd)
|
||||
#define pcmpeqd_m2r(var,reg) mmx_m2r (pcmpeqd, var, reg)
|
||||
#define pcmpeqd_r2r(regs,regd) mmx_r2r (pcmpeqd, regs, regd)
|
||||
#define pcmpeqw_m2r(var,reg) mmx_m2r (pcmpeqw, var, reg)
|
||||
#define pcmpeqw_r2r(regs,regd) mmx_r2r (pcmpeqw, regs, regd)
|
||||
|
||||
#define pcmpgtb_m2r(var,reg) mmx_m2r (pcmpgtb, var, reg)
|
||||
#define pcmpgtb_r2r(regs,regd) mmx_r2r (pcmpgtb, regs, regd)
|
||||
#define pcmpgtd_m2r(var,reg) mmx_m2r (pcmpgtd, var, reg)
|
||||
#define pcmpgtd_r2r(regs,regd) mmx_r2r (pcmpgtd, regs, regd)
|
||||
#define pcmpgtw_m2r(var,reg) mmx_m2r (pcmpgtw, var, reg)
|
||||
#define pcmpgtw_r2r(regs,regd) mmx_r2r (pcmpgtw, regs, regd)
|
||||
|
||||
#define pmaddwd_m2r(var,reg) mmx_m2r (pmaddwd, var, reg)
|
||||
#define pmaddwd_r2r(regs,regd) mmx_r2r (pmaddwd, regs, regd)
|
||||
|
||||
#define pmulhw_m2r(var,reg) mmx_m2r (pmulhw, var, reg)
|
||||
#define pmulhw_r2r(regs,regd) mmx_r2r (pmulhw, regs, regd)
|
||||
|
||||
#define pmullw_m2r(var,reg) mmx_m2r (pmullw, var, reg)
|
||||
#define pmullw_r2r(regs,regd) mmx_r2r (pmullw, regs, regd)
|
||||
|
||||
#define por_m2r(var,reg) mmx_m2r (por, var, reg)
|
||||
#define por_r2r(regs,regd) mmx_r2r (por, regs, regd)
|
||||
|
||||
#define pslld_i2r(imm,reg) mmx_i2r (pslld, imm, reg)
|
||||
#define pslld_m2r(var,reg) mmx_m2r (pslld, var, reg)
|
||||
#define pslld_r2r(regs,regd) mmx_r2r (pslld, regs, regd)
|
||||
#define psllq_i2r(imm,reg) mmx_i2r (psllq, imm, reg)
|
||||
#define psllq_m2r(var,reg) mmx_m2r (psllq, var, reg)
|
||||
#define psllq_r2r(regs,regd) mmx_r2r (psllq, regs, regd)
|
||||
#define psllw_i2r(imm,reg) mmx_i2r (psllw, imm, reg)
|
||||
#define psllw_m2r(var,reg) mmx_m2r (psllw, var, reg)
|
||||
#define psllw_r2r(regs,regd) mmx_r2r (psllw, regs, regd)
|
||||
|
||||
#define psrad_i2r(imm,reg) mmx_i2r (psrad, imm, reg)
|
||||
#define psrad_m2r(var,reg) mmx_m2r (psrad, var, reg)
|
||||
#define psrad_r2r(regs,regd) mmx_r2r (psrad, regs, regd)
|
||||
#define psraw_i2r(imm,reg) mmx_i2r (psraw, imm, reg)
|
||||
#define psraw_m2r(var,reg) mmx_m2r (psraw, var, reg)
|
||||
#define psraw_r2r(regs,regd) mmx_r2r (psraw, regs, regd)
|
||||
|
||||
#define psrld_i2r(imm,reg) mmx_i2r (psrld, imm, reg)
|
||||
#define psrld_m2r(var,reg) mmx_m2r (psrld, var, reg)
|
||||
#define psrld_r2r(regs,regd) mmx_r2r (psrld, regs, regd)
|
||||
#define psrlq_i2r(imm,reg) mmx_i2r (psrlq, imm, reg)
|
||||
#define psrlq_m2r(var,reg) mmx_m2r (psrlq, var, reg)
|
||||
#define psrlq_r2r(regs,regd) mmx_r2r (psrlq, regs, regd)
|
||||
#define psrlw_i2r(imm,reg) mmx_i2r (psrlw, imm, reg)
|
||||
#define psrlw_m2r(var,reg) mmx_m2r (psrlw, var, reg)
|
||||
#define psrlw_r2r(regs,regd) mmx_r2r (psrlw, regs, regd)
|
||||
|
||||
/* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
|
||||
(packs source and dest fields into dest in that order)
|
||||
*/
|
||||
#define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
|
||||
#define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
|
||||
#define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
|
||||
#define psubb_m2r(var,reg) mmx_m2r (psubb, var, reg)
|
||||
#define psubb_r2r(regs,regd) mmx_r2r (psubb, regs, regd)
|
||||
#define psubd_m2r(var,reg) mmx_m2r (psubd, var, reg)
|
||||
#define psubd_r2r(regs,regd) mmx_r2r (psubd, regs, regd)
|
||||
#define psubw_m2r(var,reg) mmx_m2r (psubw, var, reg)
|
||||
#define psubw_r2r(regs,regd) mmx_r2r (psubw, regs, regd)
|
||||
|
||||
#define psubsb_m2r(var,reg) mmx_m2r (psubsb, var, reg)
|
||||
#define psubsb_r2r(regs,regd) mmx_r2r (psubsb, regs, regd)
|
||||
#define psubsw_m2r(var,reg) mmx_m2r (psubsw, var, reg)
|
||||
#define psubsw_r2r(regs,regd) mmx_r2r (psubsw, regs, regd)
|
||||
|
||||
#define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
|
||||
#define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
|
||||
#define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
|
||||
#define psubusb_m2r(var,reg) mmx_m2r (psubusb, var, reg)
|
||||
#define psubusb_r2r(regs,regd) mmx_r2r (psubusb, regs, regd)
|
||||
#define psubusw_m2r(var,reg) mmx_m2r (psubusw, var, reg)
|
||||
#define psubusw_r2r(regs,regd) mmx_r2r (psubusw, regs, regd)
|
||||
|
||||
#define punpckhbw_m2r(var,reg) mmx_m2r (punpckhbw, var, reg)
|
||||
#define punpckhbw_r2r(regs,regd) mmx_r2r (punpckhbw, regs, regd)
|
||||
#define punpckhdq_m2r(var,reg) mmx_m2r (punpckhdq, var, reg)
|
||||
#define punpckhdq_r2r(regs,regd) mmx_r2r (punpckhdq, regs, regd)
|
||||
#define punpckhwd_m2r(var,reg) mmx_m2r (punpckhwd, var, reg)
|
||||
#define punpckhwd_r2r(regs,regd) mmx_r2r (punpckhwd, regs, regd)
|
||||
|
||||
#define punpcklbw_m2r(var,reg) mmx_m2r (punpcklbw, var, reg)
|
||||
#define punpcklbw_r2r(regs,regd) mmx_r2r (punpcklbw, regs, regd)
|
||||
#define punpckldq_m2r(var,reg) mmx_m2r (punpckldq, var, reg)
|
||||
#define punpckldq_r2r(regs,regd) mmx_r2r (punpckldq, regs, regd)
|
||||
#define punpcklwd_m2r(var,reg) mmx_m2r (punpcklwd, var, reg)
|
||||
#define punpcklwd_r2r(regs,regd) mmx_r2r (punpcklwd, regs, regd)
|
||||
|
||||
/* 4x16->8x8 PACK and Unsigned Saturate
|
||||
(packs source and dest fields into dest in that order)
|
||||
*/
|
||||
#define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
|
||||
#define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
|
||||
#define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
|
||||
#define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg)
|
||||
#define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd)
|
||||
|
||||
|
||||
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
|
||||
(interleaves low half of dest with low half of source
|
||||
as padding in each result field)
|
||||
*/
|
||||
#define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
|
||||
#define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
|
||||
#define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
|
||||
|
||||
#define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
|
||||
#define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
|
||||
#define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
|
||||
/* 3DNOW extensions */
|
||||
|
||||
#define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
|
||||
#define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
|
||||
#define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
|
||||
|
||||
|
||||
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
|
||||
(interleaves high half of dest with high half of source
|
||||
as padding in each result field)
|
||||
*/
|
||||
#define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
|
||||
#define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
|
||||
#define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
|
||||
#define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg)
|
||||
#define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd)
|
||||
|
||||
#define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
|
||||
#define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
|
||||
#define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
|
||||
|
||||
#define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
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||||
#define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
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||||
#define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
|
||||
|
||||
/* AMD MMX extensions - also available in intel SSE */
|
||||
|
||||
/* Empty MMx State
|
||||
(used to clean-up when going from mmx to float use
|
||||
of the registers that are shared by both; note that
|
||||
there is no float-to-mmx operation needed, because
|
||||
only the float tag word info is corruptible)
|
||||
*/
|
||||
#ifdef MMX_TRACE
|
||||
|
||||
#define emms() \
|
||||
{ \
|
||||
fprintf(stderr, "emms()\n"); \
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||||
__asm__ __volatile__ ("emms"); \
|
||||
}
|
||||
#define mmx_m2ri(op,mem,reg,imm) \
|
||||
__asm__ __volatile__ (#op " %1, %0, %%" #reg \
|
||||
: /* nothing */ \
|
||||
: "X" (mem), "X" (imm))
|
||||
#define mmx_r2ri(op,regs,regd,imm) \
|
||||
__asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \
|
||||
: /* nothing */ \
|
||||
: "X" (imm) )
|
||||
|
||||
#else
|
||||
#define mmx_fetch(mem,hint) \
|
||||
__asm__ __volatile__ ("prefetch" #hint " %0" \
|
||||
: /* nothing */ \
|
||||
: "X" (mem))
|
||||
|
||||
#define emms() __asm__ __volatile__ ("emms")
|
||||
|
||||
#endif
|
||||
#define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg)
|
||||
|
||||
#endif
|
||||
#define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var)
|
||||
|
||||
#define pavgb_m2r(var,reg) mmx_m2r (pavgb, var, reg)
|
||||
#define pavgb_r2r(regs,regd) mmx_r2r (pavgb, regs, regd)
|
||||
#define pavgw_m2r(var,reg) mmx_m2r (pavgw, var, reg)
|
||||
#define pavgw_r2r(regs,regd) mmx_r2r (pavgw, regs, regd)
|
||||
|
||||
#define pextrw_r2r(mmreg,reg,imm) mmx_r2ri (pextrw, mmreg, reg, imm)
|
||||
|
||||
#define pinsrw_r2r(reg,mmreg,imm) mmx_r2ri (pinsrw, reg, mmreg, imm)
|
||||
|
||||
#define pmaxsw_m2r(var,reg) mmx_m2r (pmaxsw, var, reg)
|
||||
#define pmaxsw_r2r(regs,regd) mmx_r2r (pmaxsw, regs, regd)
|
||||
|
||||
#define pmaxub_m2r(var,reg) mmx_m2r (pmaxub, var, reg)
|
||||
#define pmaxub_r2r(regs,regd) mmx_r2r (pmaxub, regs, regd)
|
||||
|
||||
#define pminsw_m2r(var,reg) mmx_m2r (pminsw, var, reg)
|
||||
#define pminsw_r2r(regs,regd) mmx_r2r (pminsw, regs, regd)
|
||||
|
||||
#define pminub_m2r(var,reg) mmx_m2r (pminub, var, reg)
|
||||
#define pminub_r2r(regs,regd) mmx_r2r (pminub, regs, regd)
|
||||
|
||||
#define pmovmskb(mmreg,reg) \
|
||||
__asm__ __volatile__ ("movmskps %" #mmreg ", %" #reg)
|
||||
|
||||
#define pmulhuw_m2r(var,reg) mmx_m2r (pmulhuw, var, reg)
|
||||
#define pmulhuw_r2r(regs,regd) mmx_r2r (pmulhuw, regs, regd)
|
||||
|
||||
#define prefetcht0(mem) mmx_fetch (mem, t0)
|
||||
#define prefetcht1(mem) mmx_fetch (mem, t1)
|
||||
#define prefetcht2(mem) mmx_fetch (mem, t2)
|
||||
#define prefetchnta(mem) mmx_fetch (mem, nta)
|
||||
|
||||
#define psadbw_m2r(var,reg) mmx_m2r (psadbw, var, reg)
|
||||
#define psadbw_r2r(regs,regd) mmx_r2r (psadbw, regs, regd)
|
||||
|
||||
#define pshufw_m2r(var,reg,imm) mmx_m2ri(pshufw, var, reg, imm)
|
||||
#define pshufw_r2r(regs,regd,imm) mmx_r2ri(pshufw, regs, regd, imm)
|
||||
|
||||
#define sfence() __asm__ __volatile__ ("sfence\n\t")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user